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Imporve ident of delay control assignments (#1883)
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(verilog-do-indent) Imporve ident of delay control assignments (#1883)
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my2817 authored Nov 7, 2024
1 parent 85d8429 commit 88030f2
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14 changes: 14 additions & 0 deletions tests/indent_delay_assignment.v
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module a();
always(*)begin
a = #1 b |
c |
d;
a <= #1 b |
c |
d;
a <= # 1 b |
c |
d;

end
endmodule
14 changes: 14 additions & 0 deletions tests_ok/indent_delay_assignment.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
module a();
always(*)begin
a = #1 b |
c |
d;
a <= #1 b |
c |
d;
a <= # 1 b |
c |
d;

end
endmodule
2 changes: 1 addition & 1 deletion verilog-mode.el
Original file line number Diff line number Diff line change
Expand Up @@ -7242,7 +7242,7 @@ Only look at a few lines to determine indent level."
(verilog-beg-of-statement-1)
(let ((val
(if (and (< (point) here)
(verilog-re-search-forward "=[ \t]*" here 'move)
(verilog-re-search-forward "=[ \t]*\\(#[ \t]*[0-9]+[ \t]*\\)?" here 'move)
;; not at a |=>, #=#, or [=n] operator
(not (string-match "\\[=.\\|#=#\\||=>"
(or (buffer-substring
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