Add error on misused define. (#1659)

veripool · Oct 9, 2020 · a06caa6 · a06caa6
1 parent 3b9b24f
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diff --git a/Changes b/Changes
@@ -6,10 +6,12 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilog-Perl 3.471 devel
 
-****  Add error on misused define, #1659. [Topa Tota]
+****  Add error on misused define (#1659). [Topa Tota]
 
 ****  Fix packages as enum base types, Verilator bug 2202. [Driss Hafdi]
 
+****  Fix preprocessor stringify of undefined macro (#1668). [Martin Whitaker]
+
 
 * Verilog-Perl 3.470 2020-01-06
 

diff --git a/Preproc/VPreProc.cpp b/Preproc/VPreProc.cpp
@@ -1190,8 +1190,8 @@ int VPreProcImp::getStateToken(string& buf) {
 		if (m_off) {
 		    goto next_tok;
 		} else {
-		    buf = string(yyourtext(), yyourleng());
-		    return (VP_TEXT);
+                    unputDefrefString(string("`\032") + name);
+                    goto next_tok;
 		}
 	    }
 	    else if (params=="0") {  // Found, as simple substitution

diff --git a/t/30_preproc.out b/t/30_preproc.out
@@ -884,6 +884,11 @@ verilog/inc1.v:   endgenerate
 verilog/inc1.v: endmodule
 verilog/inc1.v: 
 verilog/inc1.v: //======================================================================
+verilog/inc1.v: // Verilog-Perl bug1668
+verilog/inc1.v:  
+verilog/inc1.v: "`NOT_DEFINED_STR"
+verilog/inc1.v: 
+verilog/inc1.v: //======================================================================
 verilog/inc1.v: // IEEE mandated predefines
 verilog/inc1.v:   // undefineall should have no effect on these
 verilog/inc1.v: predef 0 0

diff --git a/t/30_preproc_nows.out b/t/30_preproc_nows.out
@@ -343,19 +343,20 @@ verilog/inc1.v:668: `line 668 "verilog/inc1.v" 0
 verilog/inc1.v:668:  initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0);
 verilog/inc1.v:669:  endgenerate
 verilog/inc1.v:670: endmodule
-verilog/inc1.v:675: predef 0 0
-verilog/inc1.v:676: predef 1 1
-verilog/inc1.v:677: predef 2 2
-verilog/inc1.v:678: predef 3 3
-verilog/inc1.v:679: predef 10 10
-verilog/inc1.v:680: predef 11 11
-verilog/inc1.v:681: predef 20 20
-verilog/inc1.v:682: predef 21 21
-verilog/inc1.v:683: predef 22 22
-verilog/inc1.v:684: predef 23 23
-verilog/inc1.v:685: predef -2 -2
-verilog/inc1.v:686: predef -1 -1
-verilog/inc1.v:687: predef 0 0
-verilog/inc1.v:688: predef 1 1
-verilog/inc1.v:689: predef 2 2
-verilog/inc1.v:691: `line 691 "verilog/inc1.v" 2
+verilog/inc1.v:675: "`NOT_DEFINED_STR"
+verilog/inc1.v:680: predef 0 0
+verilog/inc1.v:681: predef 1 1
+verilog/inc1.v:682: predef 2 2
+verilog/inc1.v:683: predef 3 3
+verilog/inc1.v:684: predef 10 10
+verilog/inc1.v:685: predef 11 11
+verilog/inc1.v:686: predef 20 20
+verilog/inc1.v:687: predef 21 21
+verilog/inc1.v:688: predef 22 22
+verilog/inc1.v:689: predef 23 23
+verilog/inc1.v:690: predef -2 -2
+verilog/inc1.v:691: predef -1 -1
+verilog/inc1.v:692: predef 0 0
+verilog/inc1.v:693: predef 1 1
+verilog/inc1.v:694: predef 2 2
+verilog/inc1.v:696: `line 696 "verilog/inc1.v" 2
diff --git a/t/30_preproc_on.out b/t/30_preproc_on.out
@@ -980,22 +980,27 @@ verilog/inc1.v:669:   endgenerate
 verilog/inc1.v:670: endmodule
 verilog/inc1.v:671: 
 verilog/inc1.v:672: //======================================================================
-verilog/inc1.v:673: // IEEE mandated predefines
-verilog/inc1.v:674:   // undefineall should have no effect on these
-verilog/inc1.v:675: predef 0 0
-verilog/inc1.v:676: predef 1 1
-verilog/inc1.v:677: predef 2 2
-verilog/inc1.v:678: predef 3 3
-verilog/inc1.v:679: predef 10 10
-verilog/inc1.v:680: predef 11 11
-verilog/inc1.v:681: predef 20 20
-verilog/inc1.v:682: predef 21 21
-verilog/inc1.v:683: predef 22 22
-verilog/inc1.v:684: predef 23 23
-verilog/inc1.v:685: predef -2 -2
-verilog/inc1.v:686: predef -1 -1
-verilog/inc1.v:687: predef 0 0
-verilog/inc1.v:688: predef 1 1
-verilog/inc1.v:689: predef 2 2
-verilog/inc1.v:690: 
-verilog/inc1.v:691: `line 691 "verilog/inc1.v" 2
+verilog/inc1.v:673: // Verilog-Perl bug1668
+verilog/inc1.v:674:  
+verilog/inc1.v:675: "`NOT_DEFINED_STR"
+verilog/inc1.v:676: 
+verilog/inc1.v:677: //======================================================================
+verilog/inc1.v:678: // IEEE mandated predefines
+verilog/inc1.v:679:   // undefineall should have no effect on these
+verilog/inc1.v:680: predef 0 0
+verilog/inc1.v:681: predef 1 1
+verilog/inc1.v:682: predef 2 2
+verilog/inc1.v:683: predef 3 3
+verilog/inc1.v:684: predef 10 10
+verilog/inc1.v:685: predef 11 11
+verilog/inc1.v:686: predef 20 20
+verilog/inc1.v:687: predef 21 21
+verilog/inc1.v:688: predef 22 22
+verilog/inc1.v:689: predef 23 23
+verilog/inc1.v:690: predef -2 -2
+verilog/inc1.v:691: predef -1 -1
+verilog/inc1.v:692: predef 0 0
+verilog/inc1.v:693: predef 1 1
+verilog/inc1.v:694: predef 2 2
+verilog/inc1.v:695: 
+verilog/inc1.v:696: `line 696 "verilog/inc1.v" 2
diff --git a/t/30_preproc_sub.out b/t/30_preproc_sub.out
@@ -1171,24 +1171,31 @@ verilog/inc1.v:670: endmodule
 verilog/inc1.v:671: 
 verilog/inc1.v:672: COMMENT: //======================================================================
 verilog/inc1.v:672:  /*CMT*/  
-verilog/inc1.v:673: COMMENT: // IEEE mandated predefines
+verilog/inc1.v:673: COMMENT: // Verilog-Perl bug1668
 verilog/inc1.v:673:  /*CMT*/  
-verilog/inc1.v:674: COMMENT: // undefineall should have no effect on these
-verilog/inc1.v:674:    /*CMT*/  
-verilog/inc1.v:675: predef DS_0 0
-verilog/inc1.v:676: predef DS_1 1
-verilog/inc1.v:677: predef DS_2 2
-verilog/inc1.v:678: predef DS_3 3
-verilog/inc1.v:679: predef DS_10 10
-verilog/inc1.v:680: predef DS_11 11
-verilog/inc1.v:681: predef DS_20 20
-verilog/inc1.v:682: predef DS_21 21
-verilog/inc1.v:683: predef DS_22 22
-verilog/inc1.v:684: predef DS_23 23
-verilog/inc1.v:685: predef DS_-2 -2
-verilog/inc1.v:686: predef DS_-1 -1
-verilog/inc1.v:687: predef DS_0 0
-verilog/inc1.v:688: predef DS_1 1
-verilog/inc1.v:689: predef DS_2 2
-verilog/inc1.v:690: 
-verilog/inc1.v:691: `line 691 "verilog/inc1.v" 2
+verilog/inc1.v:674:  
+verilog/inc1.v:675: DS_"`NOT_DEFINED_STR"
+verilog/inc1.v:676: 
+verilog/inc1.v:677: COMMENT: //======================================================================
+verilog/inc1.v:677:  /*CMT*/  
+verilog/inc1.v:678: COMMENT: // IEEE mandated predefines
+verilog/inc1.v:678:  /*CMT*/  
+verilog/inc1.v:679: COMMENT: // undefineall should have no effect on these
+verilog/inc1.v:679:    /*CMT*/  
+verilog/inc1.v:680: predef DS_0 0
+verilog/inc1.v:681: predef DS_1 1
+verilog/inc1.v:682: predef DS_2 2
+verilog/inc1.v:683: predef DS_3 3
+verilog/inc1.v:684: predef DS_10 10
+verilog/inc1.v:685: predef DS_11 11
+verilog/inc1.v:686: predef DS_20 20
+verilog/inc1.v:687: predef DS_21 21
+verilog/inc1.v:688: predef DS_22 22
+verilog/inc1.v:689: predef DS_23 23
+verilog/inc1.v:690: predef DS_-2 -2
+verilog/inc1.v:691: predef DS_-1 -1
+verilog/inc1.v:692: predef DS_0 0
+verilog/inc1.v:693: predef DS_1 1
+verilog/inc1.v:694: predef DS_2 2
+verilog/inc1.v:695: 
+verilog/inc1.v:696: `line 696 "verilog/inc1.v" 2
diff --git a/t/30_preproc_syn.out b/t/30_preproc_syn.out
@@ -964,22 +964,27 @@ verilog/inc1.v:669:   endgenerate
 verilog/inc1.v:670: endmodule
 verilog/inc1.v:671: 
 verilog/inc1.v:672: //======================================================================
-verilog/inc1.v:673: // IEEE mandated predefines
-verilog/inc1.v:674:   // undefineall should have no effect on these
-verilog/inc1.v:675: predef 0 0
-verilog/inc1.v:676: predef 1 1
-verilog/inc1.v:677: predef 2 2
-verilog/inc1.v:678: predef 3 3
-verilog/inc1.v:679: predef 10 10
-verilog/inc1.v:680: predef 11 11
-verilog/inc1.v:681: predef 20 20
-verilog/inc1.v:682: predef 21 21
-verilog/inc1.v:683: predef 22 22
-verilog/inc1.v:684: predef 23 23
-verilog/inc1.v:685: predef -2 -2
-verilog/inc1.v:686: predef -1 -1
-verilog/inc1.v:687: predef 0 0
-verilog/inc1.v:688: predef 1 1
-verilog/inc1.v:689: predef 2 2
-verilog/inc1.v:690: 
-verilog/inc1.v:691: `line 691 "verilog/inc1.v" 2
+verilog/inc1.v:673: // Verilog-Perl bug1668
+verilog/inc1.v:674:  
+verilog/inc1.v:675: "`NOT_DEFINED_STR"
+verilog/inc1.v:676: 
+verilog/inc1.v:677: //======================================================================
+verilog/inc1.v:678: // IEEE mandated predefines
+verilog/inc1.v:679:   // undefineall should have no effect on these
+verilog/inc1.v:680: predef 0 0
+verilog/inc1.v:681: predef 1 1
+verilog/inc1.v:682: predef 2 2
+verilog/inc1.v:683: predef 3 3
+verilog/inc1.v:684: predef 10 10
+verilog/inc1.v:685: predef 11 11
+verilog/inc1.v:686: predef 20 20
+verilog/inc1.v:687: predef 21 21
+verilog/inc1.v:688: predef 22 22
+verilog/inc1.v:689: predef 23 23
+verilog/inc1.v:690: predef -2 -2
+verilog/inc1.v:691: predef -1 -1
+verilog/inc1.v:692: predef 0 0
+verilog/inc1.v:693: predef 1 1
+verilog/inc1.v:694: predef 2 2
+verilog/inc1.v:695: 
+verilog/inc1.v:696: `line 696 "verilog/inc1.v" 2
diff --git a/verilog/inc1.v b/verilog/inc1.v
@@ -669,6 +669,11 @@ module pcc2_cfg;
   endgenerate
 endmodule
 
+//======================================================================
+// Verilog-Perl bug1668
+`define stringify(text) `"text`"
+`stringify(`NOT_DEFINED_STR)
+
 //======================================================================
 // IEEE mandated predefines
 `undefineall  // undefineall should have no effect on these