A summary of VHDL examples and projects.
| 📺 MINE Examples | 💽 Logic gates | ❌ |
|---|---|---|
| 📺 blink | 📺 button | 📺 first_component |
| 📺 multiple_components | ❌ | ❌ |
| 💽 gate_and | 💽 gate_or | 💽 gate_not |
| 💽 gate_nand | 💽 gate_nor | 💽 gate_xor |
| 💽 gate_xnor | 💽 gate_imply | ❌ |
- 📻 cpu_basic﹕ Design of a pentium-like 32-bit CPU.
