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[QSPI] Fixed registers and pin config on STM32U5 #460

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Jul 19, 2024
Merged

[QSPI] Fixed registers and pin config on STM32U5 #460

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24fdeb5
[QSPI] Fixed registers and pin config on STM32U5
danielinux Jun 26, 2024
52e6268
[QSPI] Fixed OCTOSPI base address on stm32u5
danielinux Jun 26, 2024
7b5012b
Cleanups from testing.
dgarske Jul 5, 2024
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2 changes: 2 additions & 0 deletions config/examples/stm32u5.config
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,8 @@ NO_ASM?=0
NO_MPU=1
EXT_FLASH?=0
SPI_FLASH?=0
QSPI_FLASH?=0
OCTOSPI_FLASH?=0
ALLOW_DOWNGRADE?=0
NVM_FLASH_WRITEONCE?=1
WOLFBOOT_VERSION?=1
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11 changes: 5 additions & 6 deletions docs/Targets.md
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Original file line number Diff line number Diff line change
Expand Up @@ -357,9 +357,7 @@ ST-LINK_gdbserver -d -cp /opt/st/stm32cubeide_1.3.0/plugins/com.st.stm32cube.ide
Max OS/X:

```sh
sudo ln -s /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.macos64_1.6.0.202101291314/tools/bin/native/mac_x64/libSTLinkUSBDriver.dylib /usr/local/lib/libSTLinkUSBDriver.dylib

/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.macos64_1.6.0.202101291314/tools/bin/ST-LINK_gdbserver -d -cp ./Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.macos64_1.6.0.202101291314/tools/bin -e -r 1 -p 3333
/Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.macos64_2.1.300.202403291623/tools/bin/ST-LINK_gdbserver -d -cp /Applications/STM32CubeIDE.app/Contents/Eclipse/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.macos64_2.1.201.202404072231/tools/bin -e -r 1 -p 3333
```

Win:
Expand All @@ -374,6 +372,7 @@ wolfBoot has a .gdbinit to configure
add-symbol-file test-app/image.elf
```


## STM32L0

Example 192KB partitioning on STM32-L073
Expand Down Expand Up @@ -2214,8 +2213,8 @@ Note:
### Running on 64-bit QEMU

Two example configuration files are available: `config/examples/x86_fsp_qemu.config` and `config/examples/x86_fsp_qemu_seal.config`.
Both will try to load a 64bit ELF/Multiboot2 payload from the emulated sata drive.
The second one is an example of configuration that also do measure boot and seal/unseal secrets using a TPM.
Both will try to load a 64bit ELF/Multiboot2 payload from the emulated sata drive.
The second one is an example of configuration that also do measure boot and seal/unseal secrets using a TPM.

A test ELF/Multiboot2 image is provided as well. To test `config/examples/x86_fsp_qemu.config` use the following steps:

Expand Down Expand Up @@ -2502,7 +2501,7 @@ To compile a flashable image run the following steps:
cp config/examples/kontron_vx3060_s2.config .config
./tools/scripts/x86_fsp/tgl/tgl_download_fsp.sh
make tpmtools
./tools/scripts/x86_fsp/tgl/assemble_image.sh -k
./tools/scripts/x86_fsp/tgl/assemble_image.sh -k
make CFLAGS_EXTRA="-DHAVE_ECC256"
./tools/scripts/x86_fsp/tgl/assemble_image.sh -n /path/to/original/flash/dump
```
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19 changes: 16 additions & 3 deletions hal/spi/spi_drv_stm32.c
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Expand Up @@ -185,8 +185,13 @@ static void stm_pins_release(void)
static void RAMFUNCTION spi_reset(void)
{
#if defined(QSPI_FLASH) || defined(OCTOSPI_FLASH)
AHB3_CLOCK_RST |= RCC_AHB3ENR_QSPIEN;
AHB3_CLOCK_RST &= ~RCC_AHB3ENR_QSPIEN;
#ifndef TARGET_stm32u5
AHB3_CLOCK_RST |= RCC_AHB3ENR_QSPIEN;
AHB3_CLOCK_RST &= ~RCC_AHB3ENR_QSPIEN;
#else
AHB2_CLOCK_RST |= RCC_AHB2ENR_QSPIEN;
AHB2_CLOCK_RST &= ~RCC_AHB2ENR_QSPIEN;
#endif
#endif
#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
APB2_CLOCK_RST |= SPI1_APB2_CLOCK_ER_VAL;
Expand Down Expand Up @@ -390,13 +395,21 @@ void RAMFUNCTION spi_init(int polarity, int phase)
if (!initialized) {
initialized++;

/* Setup clocks */
/* Setup clocks */
#if defined(QSPI_FLASH) || defined(OCTOSPI_FLASH)

#ifdef PLATFORM_stm32u5
/* Clock configuration for QSPI defaults to SYSCLK
* (RM0456 section 11.8.47)
*/
#else
/* Select QUADSPI clock source */
RCC_D1CCIPR &= ~RCC_D1CCIPR_QSPISEL_MASK;
RCC_D1CCIPR |= RCC_D1CCIPR_QSPISEL(QSPI_CLOCK_SEL);
AHB3_CLOCK_EN |= RCC_AHB3ENR_QSPIEN;
#endif
#endif

#if defined(SPI_FLASH) || defined(WOLFBOOT_TPM)
APB2_CLOCK_ER |= SPI1_APB2_CLOCK_ER_VAL;
#endif
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82 changes: 76 additions & 6 deletions hal/spi/spi_drv_stm32.h
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Original file line number Diff line number Diff line change
Expand Up @@ -40,25 +40,37 @@
#define SPI_MOSI_PIN 5 /* SPI_MOSI PB5 */
#endif /* PLATFORM_stm32f4 */


#ifdef PLATFORM_stm32u5

#ifdef TZEN
#define PERIPH_BASE (0x50000000UL)
#else
#define PERIPH_BASE (0x40000000UL)
#endif

#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02020000UL)
#define OCTOSPI1_BASE (PERIPH_BASE + 0x020D1400UL)
#define OCTOSPI2_BASE (PERIPH_BASE + 0x020D2400UL)

#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
#ifndef OCTOSPI_BASE
#define OCTOSPI_BASE OCTOSPI2_BASE
#endif

#define RCC_BASE (APB2PERIPH_BASE + 0x0C00UL)
/* Registers mapping */
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00012C00UL)
#define RCC_BASE (PERIPH_BASE + 0x06020C00UL)
#define GPIO_BASE (PERIPH_BASE + 0x02020000UL)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x02020000UL)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
#define APB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0xA4))
#define APB2_CLOCK_RST (*(volatile uint32_t *)(RCC_BASE + 0x7C))
#define AHB2_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x90))
#define AHB2_CLOCK_RST (*(volatile uint32_t *)(RCC_BASE + 0x68))

#define RCC_GPIO_CLOCK_ER (*(volatile uint32_t *)(RCC_BASE + 0x8C))

#define GPIO_BASE (APB2PERIPH_BASE + 0x02020000UL)

#define RCC_AHB2ENR_QSPIEN (1 << 8) /* OCTOSPI2 = bit 8, OCTOSPI1 = bit 4 */

#define GPIOA_BASE (GPIO_BASE + 0x00000UL)
#define GPIOB_BASE (GPIO_BASE + 0x00400UL)
#define GPIOC_BASE (GPIO_BASE + 0x00800UL)
Expand All @@ -69,6 +81,64 @@
#define GPIOH_BASE (GPIO_BASE + 0x01C00UL)
#define GPIOI_BASE (GPIO_BASE + 0x02000UL)

/** QSPI **/
/* Default Base (H) and AF (alternate function=5) for QSPI */
#define QSPI_GPIO GPIOH_BASE
#define QSPI_PIN_AF 5

#ifndef QSPI_CLOCK_BASE
#define QSPI_CLOCK_BASE 160000000
#endif

#ifndef QSPI_CLOCK_MHZ
#define QSPI_CLOCK_MHZ 10000000
#endif

/* Default to flash bank 1 */
#ifndef QSPI_FLASH_BANK
#define QSPI_FLASH_BANK 1
#endif

/* Default flash size to 16MB */
#ifndef QSPI_FLASH_SIZE
#define QSPI_FLASH_SIZE 23 /* 2^24 = 16 MB */
#endif

/* QSPI CLK PB2 (alt OCTOSPIM_P1_CLK)*/
#define QSPI_CLOCK_PIO_BASE GPIOH_BASE
#define QSPI_CLOCK_PIN 6
#define QSPI_CLOCK_PIN_AF 5

/* nQSPI_CS PG6 (alt PB6 -> OCTOSPIM_P1_NCS) */
#ifndef QSPI_ALT_CONFIGURATION
#define QSPI_CS_PIO_BASE GPIOH_BASE
#define QSPI_CS_FLASH_PIN 5
#else
#define QSPI_CS_PIO_BASE GPIOH_BASE
#define QSPI_CS_FLASH_PIN 6
#endif

/* QSPI_IO0 */
#define QSPI_IO0_PIO_BASE GPIOH_BASE
#define QSPI_IO0_PIN 9
#define QSPI_IO0_PIN_AF 5

/* QSPI_IO1 */
#define QSPI_IO1_PIO_BASE GPIOH_BASE
#define QSPI_IO1_PIN 10
#define QSPI_IO1_PIN_AF 5

/* QSPI_IO2 */
#define QSPI_IO2_PIO_BASE GPIOH_BASE
#define QSPI_IO2_PIN 11
#define QSPI_IO2_PIN_AF 5

/* QSPI_IO3 */
#define QSPI_IO3_PIO_BASE GPIOH_BASE
#define QSPI_IO3_PIN 12
#define QSPI_IO3_PIN_AF 5


/* STMOD+ Port */
#define SPI_GPIO GPIOE_BASE
#define SPI_CS_GPIO GPIOE_BASE
Expand Down
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