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RISC-V ASM: SHA-3
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Add assembly implementations of SHA-3.
Use VSRL_VX instead of two VSRL_VI operations as immediate is only 5
bits.
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SparkiDev committed Aug 29, 2024
1 parent e562a1c commit 7c3d66e
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Showing 6 changed files with 950 additions and 12 deletions.
9 changes: 9 additions & 0 deletions src/include.am
Original file line number Diff line number Diff line change
Expand Up @@ -286,6 +286,9 @@ src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/arm/armv8-32-sha3-asm
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/arm/thumb2-sha3-asm.S
endif !BUILD_ARMASM_INLINE
endif BUILD_ARMASM
if BUILD_RISCV_ASM
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/riscv/riscv-64-sha3.c
endif BUILD_RISCV_ASM
if !BUILD_X86_ASM
if BUILD_INTELASM
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/sha3_asm.S
Expand Down Expand Up @@ -447,6 +450,9 @@ src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/arm/armv8-32-sha3-asm
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/arm/thumb2-sha3-asm.S
endif !BUILD_ARMASM_INLINE
endif BUILD_ARMASM
if BUILD_RISCV_ASM
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/riscv/riscv-64-sha3.c
endif BUILD_RISCV_ASM
if BUILD_INTELASM
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/sha3_asm.S
endif
Expand Down Expand Up @@ -800,6 +806,9 @@ src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/arm/armv8-32-sha3-asm
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/arm/thumb2-sha3-asm.S
endif !BUILD_ARMASM_INLINE
endif BUILD_ARMASM
if BUILD_RISCV_ASM
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/port/riscv/riscv-64-sha3.c
endif BUILD_RISCV_ASM
if !BUILD_X86_ASM
if BUILD_INTELASM
src_libwolfssl@LIBSUFFIX@_la_SOURCES += wolfcrypt/src/sha3_asm.S
Expand Down
8 changes: 4 additions & 4 deletions wolfcrypt/src/port/riscv/riscv-64-poly1305.c
Original file line number Diff line number Diff line change
Expand Up @@ -252,10 +252,9 @@ static WC_INLINE void poly1305_blocks_riscv64_16(Poly1305* ctx,
#ifdef WOLFSSL_RISCV_VECTOR

#define MUL_RES_REDIS(l, h, t) \
VSRL_VI(t, l, 26) \
VAND_VX(l, l, REG_A6) \
VSRL_VI(t, t, 26) \
VSRL_VX(t, l, REG_A7) \
VSLL_VI(h, h, 12) \
VAND_VX(l, l, REG_A6) \
VOR_VV(h, h, t)

#endif
Expand All @@ -273,6 +272,7 @@ void poly1305_blocks_riscv64(Poly1305* ctx, const unsigned char *m,
"li a4, 0xffffffc000000\n\t"
"li a5, 0x3ffffff\n\t"
"li a6, 0xfffffffffffff\n\t"
"li a7, 52\n\t"

/* Load r and r^2 */
"mv t0, %[r2]\n\t"
Expand Down Expand Up @@ -430,7 +430,7 @@ void poly1305_blocks_riscv64(Poly1305* ctx, const unsigned char *m,
: [bytes] "+r" (bytes), [m] "+r" (m)
: [r2] "r" (ctx->r2), [h] "r" (ctx->h)
: "memory", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
"s3", "s4", "s5", "a4", "a5", "a6"
"s3", "s4", "s5", "a4", "a5", "a6", "a7"
);
#endif
poly1305_blocks_riscv64_16(ctx, m, bytes, 1);
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