RISC-V ChaCha20: assembly implementations #7818
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ChaCha20: scalar and vector implementations vector implementations doing 6, 4, 2, 1 block at a time. scalar implemetations using roriw and pack vector implementations using VROR_VI and roriw. RISC-V SHA-256: avoid using s0 if it can be helped.
SparkiDev
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retest this please |
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HiFive Unleashed at 1.4GHz: For reference here are the numbers without riscv-asm: |
dgarske
previously approved these changes
Aug 1, 2024
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Annoying. All that work and a slight regression! |
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If this is works and isn't slower than before then please merge. |
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Updated benchmarks: SHA256 17% faster. |
dgarske
approved these changes
Aug 2, 2024
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Description
ChaCha20:
scalar and vector implementations
vector implementations doing 6, 4, 2, 1 block at a time.
scalar implemetations using roriw and pack
vector implementations using VROR_VI and roriw.
RISC-V SHA-256: avoid using s0 if it can be helped.
Testing
./configure '--disable-shared' '--enable-chacha' 'LDFLAGS=--static' '--host=riscv64' 'CC=riscv64-linux-gnu-gcc' '--enable-riscv-asm'
./configure '--disable-shared' '--enable-chacha' 'LDFLAGS=--static' '--host=riscv64' 'CC=riscv64-linux-gnu-gcc' '--enable-riscv-asm=zbb'
./configure '--disable-shared' '--enable-chacha' 'LDFLAGS=--static' '--host=riscv64' 'CC=riscv64-linux-gnu-gcc' '--enable-riscv-asm=zbkb'
./configure '--disable-shared' '--enable-chacha' 'LDFLAGS=--static' '--host=riscv64' 'CC=riscv64-linux-gnu-gcc' '--enable-riscv-asm=zv'
./configure '--disable-shared' '--enable-chacha' 'LDFLAGS=--static' '--host=riscv64' 'CC=riscv64-linux-gnu-gcc' '--enable-riscv-asm=zv,zvbb'
./configure '--disable-shared' '--enable-chacha' 'LDFLAGS=--static' '--host=riscv64' 'CC=riscv64-linux-gnu-gcc' '--enable-riscv-asm=zv,zvbb,zbb'
./configure '--disable-shared' '--enable-chacha' 'LDFLAGS=--static' '--host=riscv64' 'CC=riscv64-linux-gnu-gcc' '--enable-riscv-asm=zv,zvbb,zbkb'
Checklist