Finalize v2.9.1

wwarthen · Jun 3, 2019 · b0aab77 · b0aab77
1 parent 3a1e9f3
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diff --git a/Doc/RomWBW Architecture.pdf b/Doc/RomWBW Architecture.pdf
diff --git a/ReadMe.txt b/ReadMe.txt
@@ -7,7 +7,7 @@
 ***********************************************************************
 
 Wayne Warthen (wwarthen@gmail.com)
-Version 2.9.1-pre.16, 2019-05-25
+Version 2.9.1, 2019-06-03
 https://www.retrobrewcomputers.org/
 
 RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for 
@@ -145,7 +145,7 @@ few things that UNA does not support:
 
     - Floppy Drives
     - Video/Keyboard/Terminal Emulation
-    - Zeta 1 and N8 systems
+    - Zeta 1, N8, and RC2014 systems
     - Some older support boards
     - RC2014 systems
     - Easy Z80 systems
@@ -216,7 +216,7 @@ Current inclusions are:
 	Monitor     - Z80 debug monitor with hexload capability.
 	Forth       - Brad Rodriguez's ANS compatible Forth.
 	Basic	    - Nascom 8K BASIC.
-	Tasty BASIC	- Dimitri Theulings Tiny BASIC implementation.
+	Tasty BASIC - Dimitri Theulings Tiny BASIC implementation.
 
 	Note: To exit type B in Monitor and BYE in other applications.
 

diff --git a/Source/CBIOS/ver.inc b/Source/CBIOS/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.1-pre.16"
+#DEFINE BIOSVER	"2.9.1"
diff --git a/Source/Doc/RomWBW Architecture.docx b/Source/Doc/RomWBW Architecture.docx
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
@@ -27,6 +27,11 @@ UARTENABLE	.EQU	FALSE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TR
 UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
 SIOENABLE	.EQU	FALSE		; TRUE FOR ZILOG SIO/2 SUPPORT
 SIOMODE		.EQU	SIOMODE_RC	; SIOMODE_RC, SIOMODE_SMB
+SIODEBUG	.EQU	FALSE		;PS
+DEFSIOACFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG
+DEFSIOBCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG
+DEFSIODIV	.EQU	1		; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5
+DEFSIOCLK	.EQU	7372800		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY
 ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
 ;
 VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT

diff --git a/Source/HBIOS/dsky.asm b/Source/HBIOS/dsky.asm
@@ -262,11 +262,11 @@ DSKY_HEXOUT1:
 DSKY_SHOWHEX:
 	LD	A,$D0			; 7218 -> (DATA COMING, HEXA DECODE)
 	JR	DSKY_SHOW
-
+;
 DSKY_SHOWSEG:
 	LD	A,$F0			; 7218 -> (DATA COMING, NO DECODE)
 	JR	DSKY_SHOW
-
+;
 DSKY_SHOW:
 	PUSH	AF			; SAVE 7218 CONTROL BITS
 	LD	A,82H			; SETUP PPI
@@ -290,15 +290,37 @@ DSKY_STROBE:	; DATA STROBE
 DSKY_STROBE0:
 	OUT	(PPIC),A		; OUT TO PORTC
 	CALL	DLY2			; DELAY
-DSKY_COFF
+DSKY_COFF:
 	LD	A,40H | 30H		; QUIESCE
 	OUT	(PPIC),A		; OUT TO PORTC
 ;	CALL	DSKY_DELAY		; WAIT
 	RET
 ;
+; CODES FOR NUMERICS
+; HIGH BIT ALWAYS SET TO SUPPRESS DECIMAL POINT
+; CLEAR HIGH BIT TO SHOW DECIMAL POINT
+;
+DSKY_NUMS:
+	.DB	$FB	; 0
+	.DB	$B0	; 1
+	.DB	$ED	; 2
+	.DB	$F5	; 3
+	.DB	$B6	; 4
+	.DB	$D7	; 5
+	.DB	$DF	; 6
+	.DB	$F0	; 7
+	.DB	$FF	; 8
+	.DB	$F7	; 9
+	.DB	$FE	; A
+	.DB	$9F	; B
+	.DB	$CB	; C
+	.DB	$BD	; D
+	.DB	$CF	; E
+	.DB	$CE	; F
+;
 ; SEG DISPLAY WORKING STORAGE
 ;
-DSKY_BUF:	.FILL	8,0
+DSKY_BUF	.FILL	8,0
 DSKY_BUFLEN	.EQU	$ - DSKY_BUF
 DSKY_HEXBUF	.FILL	4,0
 DSKY_HEXBUFLEN	.EQU	$ - DSKY_HEXBUF
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
@@ -144,7 +144,7 @@ ROM_SIG:
 ;
 NAME	.DB	"ROMWBW v", BIOSVER, ", ", TIMESTAMP, 0
 AUTH	.DB	"WBW",0
-DESC	.DB	"ROMWBW v", BIOSVER, ", Copyright (C) 2015, Wayne Warthen, GNU GPL v3", 0
+DESC	.DB	"ROMWBW v", BIOSVER, ", Copyright (C) 2019, Wayne Warthen, GNU GPL v3", 0
 ;
 	.FILL	($100 - $),$FF		; PAD REMAINDER OF PAGE ZERO
 ;
@@ -942,6 +942,17 @@ HB_START1:				; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK
 	DIAG(%00001111)
 ;
 #IF (DSKYENABLE)
+	LD	HL,MSG_HBVER +  5
+	LD	A,(DSKY_NUMS + RMJ)
+	AND	$7F
+	LD	(HL),A
+	INC	HL
+	LD	A,(DSKY_NUMS + RMN)
+	AND	$7F
+	LD	(HL),A
+	INC	HL
+	LD	A,(DSKY_NUMS + RUP)
+	LD	(HL),A
 	LD	HL,MSG_HBVER
 	CALL	DSKY_SHOWSEG
 #ENDIF
@@ -3720,8 +3731,9 @@ STR_PLATFORM	.DB	PLATFORM_NAME, "$"
 STR_SWITCH	.DB	"*** Activating CRT Console ***$"
 STR_BADINT	.DB	"\r\n*** BAD INT ***\r\n$"
 ;
-#IF (DSKYENABLE)
-MSG_HBVER		.DB	$BE,$FF,$8A,$FB,$D7,$6D,$77,$B0	; "HBIOS291"
+#IF (DSKYENABLE)	;	'H','B','I','O',' ','2','9','1'
+;MSG_HBVER		.DB	$BE,$FF,$8A,$FB,$80,$6D,$77,$B0	; "HBIO 291"
+MSG_HBVER		.DB	$BE,$FF,$8A,$FB,$80,$80,$80,$80	; "HBIO    "
 #ENDIF
 ;
 HB_CURSEC	.DB	0		; CURRENT SECOND (TEMP)

diff --git a/Source/HBIOS/plt_rcz180.inc b/Source/HBIOS/plt_rcz180.inc
@@ -12,4 +12,6 @@ MPGENA		.EQU	$7C		; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 RTC		.EQU	$0C		; ADDRESS OF RTC LATCH AND INPUT PORT
 ;
 Z180_BASE	.EQU	$C0		; I/O BASE ADDRESS FOR INTERNAL Z180 REGISTERS
+SIOBASE 	.EQU 	$80 		; RC OR SMB SIO DEFAULT
+;
 #INCLUDE "z180.inc"
diff --git a/Source/HBIOS/plt_rcz80.inc b/Source/HBIOS/plt_rcz80.inc
@@ -8,4 +8,4 @@ MPGSEL_3	.EQU	$7B	; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
 MPGENA		.EQU	$7C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 ;
 RTC	    	.EQU	$C0	; RTC PORT address
-SIOBASE 	.EQU 	$80 ; RC OR SMB SIO DEFAULT
+SIOBASE 	.EQU 	$80 	; RC OR SMB SIO DEFAULT
diff --git a/Source/HBIOS/ver.inc b/Source/HBIOS/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.1-pre.16"
+#DEFINE BIOSVER	"2.9.1"