A FIFO or Queue is an array of memory to transfer transfer data between two circuits with different clocks. FIFO uses a dual port memory and there will be two pointers to point read and write addresses.More information.
- Full: high when FIFO is full.
- Empty: high when FIFO is empty.
Counter will be incremented if:
- Write takes place and buffer is not full.
Counter will be decremented if:
- Read takes place and buffer is not empty.
π«π«π« If both read and write takes place, counter will remain the same.
This project needs Icarus-Verilog and a VCD viewer.
- Icarus-Verilog can be installed via Homebrew :
$ brew install icarus-verilog
- Download Scansion from here.
- Clone the repository.
- Change the directory to src.
$ make simulate
will:
- compile design+TB
- simulate the verilog design
$ make display
will:
- display waveforms.