Electronics Enthusiast
| VLSI | Embedded Systems
-
Purdue University
- West Lafayette
-
04:46
(UTC -05:00) - www.yatharthagarwal.net
Pinned Loading
-
FemtoRV_RISCV
FemtoRV_RISCV PublicRISCV32I single core processor with UART implemented on the ARTIX7 FPGA
C 1
-
-
Physical_Verification_SKY130A
Physical_Verification_SKY130A PublicUnderstanding Physical Verification using open source tools such as Magic and Netgen
-
VSDSquadron
VSDSquadron PublicSchematics and images for the VSDSquadron board series, crafted to make RISC-V education accessible and engaging for learners at all levels. This board family is tailored to simplify the learning p…
Batchfile
-
BrunoLevy/learn-fpga
BrunoLevy/learn-fpga PublicLearning FPGA, yosys, nextpnr, and RISC-V
-
The-OpenROAD-Project/OpenROAD-flow-scripts
The-OpenROAD-Project/OpenROAD-flow-scripts PublicOpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.