Electronics Enthusiast
| VLSI | Embedded Systems
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Purdue University
- West Lafayette
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19:19
(UTC -05:00) - www.yatharthagarwal.net
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FemtoRV_RISCV
FemtoRV_RISCV PublicRISCV32I single core processor with UART implemented on the ARTIX7 FPGA
C 1
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Physical_Verification_SKY130A
Physical_Verification_SKY130A PublicUnderstanding Physical Verification using open source tools such as Magic and Netgen
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VSDSquadron
VSDSquadron PublicSchematics and images for the VSDSquadron board series, crafted to make RISC-V education accessible and engaging for learners at all levels. This board family is tailored to simplify the learning p…
Batchfile
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BrunoLevy/learn-fpga
BrunoLevy/learn-fpga PublicLearning FPGA, yosys, nextpnr, and RISC-V
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The-OpenROAD-Project/OpenROAD-flow-scripts
The-OpenROAD-Project/OpenROAD-flow-scripts PublicOpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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