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Releases: yuchangyuan/chisel2verilog

SIF image of v0.4

30 Sep 04:11
@yuchangyuan yuchangyuan
v0.4
c90ea01
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SIF image of v0.4 Pre-release
Pre-release 
up to v0.4
Assets 3
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SIF image of v0.3

09 Jul 11:21
@yuchangyuan yuchangyuan
v0.3
0045cd7
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SIF image of v0.3 Pre-release
Pre-release
  • chisel version: 5.0.0
  • scala version: 2.13.10
Assets 3
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SIF image build with v0.2 source

09 Jul 09:32
@yuchangyuan yuchangyuan
v0.2
0fdbf50
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SIF image build with v0.2 source Pre-release
Pre-release
  • chisel version org.chipsalliance::chisel:5.0.0-RC2
  • scala version 2.13
Assets 3
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