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18 Open 255 Closed
18 Open 255 Closed
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Issues list

Generate _sv2v_0 problem
#293 opened Oct 21, 2024 by BoChen-Ye
1
add enum attributes to enum values
#292 opened Oct 11, 2024 by rroohhh
2
Assert Property disable iff not fully converted to Verilog
#289 opened Jul 10, 2024 by HakamAtassi
2
Integration with SVase?!
#286 opened Jun 15, 2024 by chili-chips-ba
6
regarding system verilog to verilog
#280 opened Apr 13, 2024 by sundeep2249
8
Add support for disable statement
#278 opened Feb 29, 2024 by spth
4
Automatic Function Produces Construct with Infinite Loop in Yosys
#275 opened Jan 23, 2024 by wrs225
4
Mutidimensional Packed Arrays Handler Does Not Match Commercial Synthesis Tools
#271 opened Jan 17, 2024 by sifferman
1
Different types in generate branches results in error
#265 opened Nov 30, 2023 by mole99
2
Would you please implement those enum methods for SystemVerilog ?
#263 opened Nov 16, 2023 by forthyen
1
Array literals flow into Verilog unchanged
#260 opened Nov 2, 2023 by YikeZhou
[feature request] support for field name preservation when struct conversion
#253 opened Aug 28, 2023 by Dragon-Git
6
expanded interface instance
#230 opened Feb 25, 2023 by michael-lehn
3
Array manipulation methods
#219 opened Sep 23, 2022 by daglem
1
illegal statements with interfaces which do not either raise an error, or generate valid verilog
#206 opened May 8, 2022 by hughperkins
4
always_comb allows <=, always_ff allows =
#198 opened Mar 15, 2022 by hughperkins
3
Question: how do you handle relating error messages to the original systemverilog source code?
#194 opened Feb 25, 2022 by hughperkins
5
Classes as namespaces not supported?
#97 opened Jun 19, 2020 by fl4shk
10
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