GitHub - zarelit/DSD-CRC-VHDL: CRC module in VHDL (Digital Systems Design class assignment)

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CRC module in VHDL (Digital Systems Design class assignment)

Name		Name	Last commit message	Last commit date
Latest commit History 134 Commits
CRC Logic Modules		CRC Logic Modules
TestBenches		TestBenches
doc		doc
CRC_Logic.vhd		CRC_Logic.vhd
CRC_control.vhd		CRC_control.vhd
README		README
RX_nopreload.asdb		RX_nopreload.asdb
RX_nopreload.awc		RX_nopreload.awc
RX_preload.asdb		RX_preload.asdb
RX_preload.awc		RX_preload.awc
TX_nopreload.asdb		TX_nopreload.asdb
TX_nopreload.awc		TX_nopreload.awc
TX_preload.asdb		TX_preload.asdb
TX_preload.awc		TX_preload.awc
crc_module_tb_NO_PRELOAD_conf.vhd		crc_module_tb_NO_PRELOAD_conf.vhd
crc_module_tb_RX_NOPRELOAD.vhd		crc_module_tb_RX_NOPRELOAD.vhd
crc_module_tb_conf.vhd		crc_module_tb_conf.vhd
crc_module_tb_rx_preload.vhd		crc_module_tb_rx_preload.vhd
crc_top.vhd		crc_top.vhd
md_selector.vhd		md_selector.vhd
multiplexer.vhd		multiplexer.vhd
preload_conf_crc_control.vhd		preload_conf_crc_control.vhd
shif_reg.vhd		shif_reg.vhd

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