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103 followers · 24 following

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Achievement: YOLOAchievement: StarstruckAchievement: Pull Sharkx2Achievement: Arctic Code Vault Contributor

Achievements

Achievement: YOLOAchievement: StarstruckAchievement: Pull Sharkx2Achievement: Arctic Code Vault Contributor

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@merledu @ShaheenRV

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zeeshanrafique23/README.md

Hi there! My name is Zeeshan Rafique.

"RTL Design and Verification Engineer"

I am an RTL design and Verification engineer with a strong background in Computer Architecture and Digital Logic Design. I have deep knowledge of System on Chip components like bus protocols and peripheral communication with CPU. My research focus area is to improve computation speed and power optimization in hardware for Machine Learning applications.

💻 Languages:

  • SystemVerilog, Verilog, CHISEL
  • Universal Verification Methodology (UVM)
  • RISC-V Assembly
  • C / C++
  • Python, Bash, tcl

🖲️ Tools:

  • Xcelium, Questa Sim, Vivado (xsim), Verilator, iCarus Verilog, GTK wave
  • Vivado (synthesis and implementation), AWS Cloud FPGA
  • Genus, Yosys

Pinned Loading

  1. mdu mdu Public

    M-extension for RISC-V cores.

    Verilog 22 9

  2. opentitan opentitan Public

    Forked from lowRISC/opentitan

    OpenTitan: Open source silicon root of trust

    SystemVerilog

  3. merledu/azadi-soc merledu/azadi-soc Public

    Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

    SystemVerilog 26 9

  4. ibex ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog

  5. RV32I-Logisim RV32I-Logisim Public

    RV32I single cycle simulation on open-source software Logisim.

    16 10

  6. serv serv Public

    Forked from olofk/serv

    SERV - The SErial RISC-V CPU

    Verilog