hal: bump sync/release_v5.1.c

Sync hal_espressif to the following SHA:

98cd3582cc65b874a26b35165449aa40331fe199
(Aug 22, 2024)

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>

components/bootloader/Kconfig.projbuild

@@ -62,34 +62,66 @@ menu "Bootloader config"
         default 4 if BOOTLOADER_LOG_LEVEL_DEBUG
         default 5 if BOOTLOADER_LOG_LEVEL_VERBOSE
 
-    config BOOTLOADER_SPI_CUSTOM_WP_PIN
-        bool "Use custom SPI Flash WP Pin when flash pins set in eFuse (read help)"
-        depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)
-        default y if BOOTLOADER_SPI_WP_PIN != 7  # backwards compatibility, can remove in IDF 5
-        default n
-        help
-            This setting is only used if the SPI flash pins have been overridden by setting the eFuses
-            SPI_PAD_CONFIG_xxx, and the SPI flash mode is QIO or QOUT.
-
-            When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
-            ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The same pin is also used
-            for external SPIRAM if it is enabled.
-
-            If this config item is set to N (default), the correct WP pin will be automatically used for any
-            Espressif chip or module with integrated flash. If a custom setting is needed, set this config item to
-            Y and specify the GPIO number connected to the WP.
-
-    config BOOTLOADER_SPI_WP_PIN
-        int "Custom SPI Flash WP Pin"
-        range 0 33
-        default 7
-        depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)
-        #depends on BOOTLOADER_SPI_CUSTOM_WP_PIN  # backwards compatibility, can uncomment in IDF 5
-        help
-            The option "Use custom SPI Flash WP Pin" must be set or this value is ignored
+    menu "Serial Flash Configurations"
+        config BOOTLOADER_SPI_CUSTOM_WP_PIN
+            bool "Use custom SPI Flash WP Pin when flash pins set in eFuse (read help)"
+            depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)
+            default y if BOOTLOADER_SPI_WP_PIN != 7  # backwards compatibility, can remove in IDF 5
+            default n
+            help
+                This setting is only used if the SPI flash pins have been overridden by setting the eFuses
+                SPI_PAD_CONFIG_xxx, and the SPI flash mode is QIO or QOUT.
+
+                When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka
+                ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The same pin is also used
+                for external SPIRAM if it is enabled.
+
+                If this config item is set to N (default), the correct WP pin will be automatically used for any
+                Espressif chip or module with integrated flash. If a custom setting is needed, set this config item to
+                Y and specify the GPIO number connected to the WP.
+
+        config BOOTLOADER_SPI_WP_PIN
+            int "Custom SPI Flash WP Pin"
+            range 0 33
+            default 7
+            depends on IDF_TARGET_ESP32 && (ESPTOOLPY_FLASHMODE_QIO || ESPTOOLPY_FLASHMODE_QOUT)
+            #depends on BOOTLOADER_SPI_CUSTOM_WP_PIN  # backwards compatibility, can uncomment in IDF 5
+            help
+                The option "Use custom SPI Flash WP Pin" must be set or this value is ignored
 
-            If burning a customized set of SPI flash pins in eFuse and using QIO or QOUT mode for flash, set this
-            value to the GPIO number of the SPI flash WP pin.
+                If burning a customized set of SPI flash pins in eFuse and using QIO or QOUT mode for flash, set this
+                value to the GPIO number of the SPI flash WP pin.
+
+        config BOOTLOADER_FLASH_DC_AWARE
+            bool "Allow app adjust Dummy Cycle bits in SPI Flash for higher frequency (READ HELP FIRST)"
+            help
+                This will force 2nd bootloader to be loaded by DOUT mode, and will restore Dummy Cycle setting by
+                resetting the Flash
+
+        config BOOTLOADER_FLASH_XMC_SUPPORT
+            bool "Enable the support for flash chips of XMC (READ DOCS FIRST)"
+            default y
+            help
+                Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow.
+                XMC chips will be forbidden to be used, when this option is disabled.
+
+                DON'T DISABLE THIS UNLESS YOU KNOW WHAT YOU ARE DOING.
+
+                comment "Features below require specific hardware (READ DOCS FIRST!)"
+
+        config BOOTLOADER_FLASH_32BIT_ADDR
+            bool
+            default y if ESPTOOLPY_FLASHSIZE_32MB || ESPTOOLPY_FLASHSIZE_64MB || ESPTOOLPY_FLASHSIZE_128MB
+            default n
+            help
+                This is a helper config for 32bits address flash. Invisible for users.
+
+        config BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
+            bool
+            default y if ESPTOOLPY_OCT_FLASH && BOOTLOADER_FLASH_32BIT_ADDR
+            default n
+
+    endmenu
 
     choice BOOTLOADER_VDDSDIO_BOOST
         bool "VDDSDIO LDO voltage"
@@ -405,6 +437,21 @@ menu "Bootloader config"
             (The application and bootoloader must be compiled with the same option).
             The RTC FAST memory has access only through PRO_CPU.
 
+    config BOOTLOADER_CUSTOM_RESERVE_RTC_IN_CRC
+        bool "Include custom memory in the CRC calculation"
+        depends on BOOTLOADER_CUSTOM_RESERVE_RTC
+        default n
+        help
+            This option allows the customer to use the legacy bootloader behavior when the
+            RTC FAST memory CRC calculation takes place. When this option is enabled, the
+            allocated user custom data will be taken into account in the CRC calculcation.
+            This means that any change to the custom data would need a CRC update to prevent
+            the bootloader from marking this data as corrupted.
+            If this option is disabled, the custom data will not be taken into account when
+            calculating the RTC FAST memory CRC. The user custom data can be changed freely,
+            without the need to update the CRC.
+            THIS OPTION MUST BE THE SAME FOR BOTH THE BOOTLOADER AND THE APPLICATION BUILDS.
+
     config BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE
         hex "Size in bytes for custom purposes"
         default 0
@@ -424,15 +471,6 @@ menu "Bootloader config"
             - "Reserve RTC FAST memory for custom purposes"
             - "GPIO triggers factory reset"
 
-    config BOOTLOADER_FLASH_XMC_SUPPORT
-        bool "Enable the support for flash chips of XMC (READ HELP FIRST)"
-        default y
-        help
-            Perform the startup flow recommended by XMC. Please consult XMC for the details of this flow.
-            XMC chips will be forbidden to be used, when this option is disabled.
-
-            DON'T DISABLE THIS UNLESS YOU KNOW WHAT YOU ARE DOING.
-
 endmenu  # Bootloader
 
 
@@ -704,14 +742,12 @@ menu "Security features"
 
     config SECURE_BOOT_VERIFICATION_KEY
         string "Secure boot public signature verification key"
-        depends on SECURE_SIGNED_APPS && !SECURE_BOOT_BUILD_SIGNED_BINARIES && !SECURE_SIGNED_APPS_RSA_SCHEME
+        depends on SECURE_SIGNED_APPS && SECURE_SIGNED_APPS_ECDSA_SCHEME && !SECURE_BOOT_BUILD_SIGNED_BINARIES
         default "signature_verification_key.bin"
         help
             Path to a public key file used to verify signed images.
             Secure Boot V1: This ECDSA public key is compiled into the bootloader and/or
             app, to verify app images.
-            Secure Boot V2: This RSA public key is compiled into the signature block at
-            the end of the bootloader/app.
 
             Key file is in raw binary format, and can be extracted from a
             PEM formatted private key using the espsecure.py
@@ -1009,6 +1045,22 @@ menu "Security features"
                 DIS_DOWNLOAD_MANUAL_ENCRYPT, DIS_USB_JTAG, DIS_USB_SERIAL_JTAG, STRAP_JTAG_SEL, USB_PHY_SEL.
     endmenu  # Potentially Insecure
 
+    config SECURE_FLASH_ENCRYPT_ONLY_IMAGE_LEN_IN_APP_PART
+        bool "Encrypt only the app image that is present in the partition of type app"
+        depends on SECURE_FLASH_ENC_ENABLED && !SECURE_FLASH_REQUIRE_ALREADY_ENABLED
+        default n
+        help
+            If set, optimise encryption time for the partition of type APP,
+            by only encrypting the app image that is present in the partition,
+            instead of the whole partition.
+            The image length used for encryption is derived from the image metadata, which
+            includes the size of the app image, checksum, hash and also the signature sector
+            when secure boot is enabled.
+
+            If not set (default), the whole partition of type APP would be encrypted,
+            which increases the encryption time but might be useful if there
+            is any custom data appended to the firmware image.
+
     config SECURE_FLASH_CHECK_ENC_EN_IN_APP
         bool "Check Flash Encryption enabled on app startup"
         depends on SECURE_FLASH_ENC_ENABLED

components/bootloader/sdkconfig.rename

@@ -23,3 +23,5 @@ CONFIG_FLASH_ENCRYPTION_UART_BOOTLOADER_ALLOW_CACHE         CONFIG_SECURE_FLASH_
 
 # Secure Boot Scheme
 CONFIG_SECURE_BOOT_ENABLED                                  CONFIG_SECURE_BOOT_V1_ENABLED
+
+CONFIG_SPI_FLASH_OCTAL_32BIT_ADDR_ENABLE                    CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH

components/bootloader_support/bootloader_flash/include/bootloader_flash.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -54,6 +54,13 @@ esp_err_t bootloader_flash_reset_chip(void);
  */
 bool bootloader_flash_is_octal_mode_enabled(void);
 
+/**
+ * @brief Get the spi flash working mode.
+ *
+ * @return The mode of flash working mode, see `esp_rom_spiflash_read_mode_t`
+ */
+esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void);
+
 #ifdef __cplusplus
 }
 #endif

components/bootloader_support/bootloader_flash/include/bootloader_flash_override.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -109,6 +109,17 @@ extern const bootloader_qio_info_t __attribute__((weak)) bootloader_flash_qe_sup
   */
 esp_err_t __attribute__((weak)) bootloader_flash_unlock(void);
 
+#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
+/**
+ * @brief Enable 32bits address flash(larger than 16MB) can map to cache.
+ *
+ * @param flash_mode SPI flash working mode.
+ *
+ * @note This can be overridden because it's attribute weak.
+ */
+void __attribute__((weak)) bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t flash_mode);
+#endif
+
 #ifdef __cplusplus
 }
 #endif

components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h

@@ -52,6 +52,8 @@ extern "C" {
 #define CMD_RESUME     0x7A /* Resume command to clear flash suspend bit */
 #define CMD_RESETEN    0x66
 #define CMD_RESET      0x99
+#define CMD_FASTRD_4B       0x0C
+#define CMD_SLOWRD_4B       0x13
 
 
 /* Provide a Flash API for bootloader_support code,

components/bootloader_support/bootloader_flash/src/bootloader_flash.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -124,6 +124,9 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
 #include "hal/mmu_hal.h"
 #include "hal/mmu_ll.h"
 #include "hal/cache_hal.h"
+#if CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/opi_flash.h"
+#endif
 static const char *TAG = "bootloader_flash";
 
 #if CONFIG_IDF_TARGET_ESP32
@@ -414,6 +417,33 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
     return spi_to_esp_err(rc);
 }
 
+#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
+void bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t flash_mode)
+{
+    esp_rom_opiflash_spi0rd_t cache_rd = {};
+    switch (flash_mode) {
+    case ESP_ROM_SPIFLASH_FASTRD_MODE:
+        cache_rd.addr_bit_len = 32;
+        cache_rd.dummy_bit_len = 8;
+        cache_rd.cmd = CMD_FASTRD_4B;
+        cache_rd.cmd_bit_len = 8;
+        break;
+     case ESP_ROM_SPIFLASH_SLOWRD_MODE:
+        cache_rd.addr_bit_len = 32;
+        cache_rd.dummy_bit_len = 0;
+        cache_rd.cmd = CMD_SLOWRD_4B;
+        cache_rd.cmd_bit_len = 8;
+        break;
+    default:
+        assert(false);
+        break;
+    }
+    cache_hal_disable(CACHE_TYPE_ALL);
+    esp_rom_opiflash_cache_mode_config(flash_mode, &cache_rd);
+    cache_hal_enable(CACHE_TYPE_ALL);
+}
+#endif
+
 #endif // BOOTLOADER_BUILD
 
 
@@ -760,3 +790,40 @@ bool IRAM_ATTR bootloader_flash_is_octal_mode_enabled(void)
     return false;
 #endif
 }
+
+esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void)
+{
+    esp_rom_spiflash_read_mode_t spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
+#if CONFIG_IDF_TARGET_ESP32
+    uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));
+    if (spi_ctrl & SPI_FREAD_QIO) {
+        spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;
+    } else if (spi_ctrl & SPI_FREAD_QUAD) {
+        spi_mode = ESP_ROM_SPIFLASH_QOUT_MODE;
+    } else if (spi_ctrl & SPI_FREAD_DIO) {
+        spi_mode = ESP_ROM_SPIFLASH_DIO_MODE;
+    } else if (spi_ctrl & SPI_FREAD_DUAL) {
+        spi_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
+    } else if (spi_ctrl & SPI_FASTRD_MODE) {
+        spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
+    } else {
+        spi_mode = ESP_ROM_SPIFLASH_SLOWRD_MODE;
+    }
+#else
+    uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
+    if (spi_ctrl & SPI_MEM_FREAD_QIO) {
+        spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;
+    } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
+        spi_mode = ESP_ROM_SPIFLASH_QOUT_MODE;
+    } else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
+        spi_mode = ESP_ROM_SPIFLASH_DIO_MODE;
+    } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
+        spi_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
+    } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
+        spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
+    } else {
+        spi_mode = ESP_ROM_SPIFLASH_SLOWRD_MODE;
+    }
+#endif
+    return spi_mode;
+}

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c

@@ -260,7 +260,7 @@ esp_err_t bootloader_init_spi_flash(void)
     }
 #endif
 
-#if CONFIG_SPI_FLASH_HPM_ENABLE
+#if CONFIG_BOOTLOADER_FLASH_DC_AWARE
     // Reset flash, clear volatile bits DC[0:1]. Make it work under default mode to boot.
     bootloader_spi_flash_reset();
 #endif
@@ -272,7 +272,9 @@ esp_err_t bootloader_init_spi_flash(void)
         bootloader_enable_qio_mode();
     }
 #endif
-
+#if CONFIG_BOOTLOADER_CACHE_32BIT_ADDR_OCTAL_FLASH
+    bootloader_flash_32bits_address_map_enable(bootloader_flash_get_spi_mode());
+#endif
     print_flash_info(&bootloader_image_hdr);
     update_flash_config(&bootloader_image_hdr);
     //ensure the flash is write-protected

components/bootloader_support/include/esp_image_format.h

@@ -33,6 +33,7 @@ typedef struct {
   uint32_t segment_data[ESP_IMAGE_MAX_SEGMENTS]; /* Data offsets for each segment */
   uint32_t image_len; /* Length of image on flash, in bytes */
   uint8_t image_digest[32]; /* appended SHA-256 digest */
+  uint32_t secure_version; /* secure version for anti-rollback, it is covered by sha256 (set if CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK=y) */
 } esp_image_metadata_t;
 
 typedef enum {

components/bootloader_support/include/esp_secure_boot.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -282,6 +282,23 @@ esp_err_t esp_secure_boot_enable_secure_features(void);
  */
 bool esp_secure_boot_cfg_verify_release_mode(void);
 
+
+#if !defined(BOOTLOADER_BUILD) && SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY && CONFIG_SECURE_BOOT_V2_ENABLED
+
+/** @brief Returns the verification status of the image pointed by the part_pos argument against the public key digest present at index `efuse_digest_index`
+ *
+ * @param index[in]         Index of public key digest present in efuse against which the image is to be verified
+ * @param part_pos[in]      It is a pointer to the bootloader/app partition.
+ *
+ * @return
+ *  - ESP_OK - if the image can be verified by the key at efuse_index.
+ *  - ESP_FAIL - if the image cannot be verified by the key at efuse_index.
+ *  - ESP_ERR_INVALID_ARG: Error in the passed arguments.
+ */
+esp_err_t esp_secure_boot_verify_with_efuse_digest_index(int efuse_digest_index, esp_partition_pos_t *part_pos);
+
+#endif // !defined(BOOTLOADER_BUILD) && SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY && CONFIG_SECURE_BOOT_V2_ENABLED
+
 #ifdef __cplusplus
 }
 #endif

components/bootloader_support/src/bootloader_common_loader.c

@@ -122,7 +122,7 @@ int bootloader_common_select_otadata(const esp_ota_select_entry_t *two_otadata,
 #if CONFIG_BOOTLOADER_RESERVE_RTC_MEM
 
 static uint32_t rtc_retain_mem_size(void) {
-#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
+#if CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC && !CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_IN_CRC
     /* A custom memory has been reserved by the user, do not consider this memory into CRC calculation as it may change without
      * the have the user updating the CRC. Return the offset of the custom field, which is equivalent to size of the structure
      * minus the size of everything after (including) `custom` */