s32: soc: s32z2: add QSPI soc specific code

Code autogenerated with S32 Design Studio for s32ze

Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>

s32/soc/s32z270/include/Qspi_Ip_Cfg.h

@@ -0,0 +1,115 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QSPI_IP_CFG_H
+#define QSPI_IP_CFG_H
+
+/**
+*   @file Qspi_Ip_Cfg.h
+*
+*   @addtogroup MEM_EXFLS
+*   Qspi_Ip_Cfg.h_Artifact
+*   @{
+*/
+
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Qspi_Ip_Types.h"
+
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define QSPI_IP_VENDOR_ID_CFG                    43
+#define QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG     4
+#define QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG     7
+#define QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG  0
+#define QSPI_IP_SW_MAJOR_VERSION_CFG             2
+#define QSPI_IP_SW_MINOR_VERSION_CFG             0
+#define QSPI_IP_SW_PATCH_VERSION_CFG             0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       DEFINES AND MACROS
+==================================================================================================*/
+
+/* Number of serial flash devices */
+#define QSPI_IP_MEM_INSTANCE_COUNT        (1U)
+
+/* Maximum number of retries for Write Enable command */
+#define QSPI_IP_MAX_RETRY                 (3U)
+
+/* Development error detection for QSPI Ip API */
+#define QSPI_IP_DEV_ERROR_DETECT          (STD_OFF)
+
+/* Timeout for DLL lock sequence */
+#define QSPI_IP_DLL_LOCK_TIMEOUT          (10000000U)
+
+/* Timeout for QSPI command completion */
+#define QSPI_IP_CMD_COMPLETE_TIMEOUT      (10000000U)
+
+/* After the FRAD checks pass we wait for QSPI to become idle */
+#define QSPI_IP_QSPI_IDLE_TIMEOUT         (100U)
+
+/* Timeout for external flash software reset completion */
+#define QSPI_IP_RESET_TIMEOUT             (2000000U)
+
+/* Timeout for external flash startup initialization sequence completion */
+#define QSPI_IP_FLS_INIT_TIMEOUT          (2000000U)
+
+/* Timeout for a complete read operation */
+#define QSPI_IP_READ_TIMEOUT              (2147483647U)
+
+/* OsIf counter type used in timeout detection for QSPI IP operations  */
+#define QSPI_IP_TIMEOUT_TYPE              (OSIF_COUNTER_DUMMY)
+
+/* Delay after changing the value of the QSPI software reset bits */
+#define QSPI_IP_SOFTWARE_RESET_DELAY      (21U)
+
+/*! @brief Minimum delay in CPU cycles between Tx FIFO reset and Tx FIFO push */
+#define QSPI_IP_TX_BUFFER_RESET_DELAY     (0U)
+
+
+/* QSPI user mode support macro */
+#define QSPI_IP_ENABLE_USER_MODE_SUPPORT  (STD_OFF)
+
+#ifndef MCAL_ENABLE_USER_MODE_SUPPORT
+    #if (STD_ON == QSPI_IP_ENABLE_USER_MODE_SUPPORT)
+        #error MCAL_ENABLE_USER_MODE_SUPPORT is not enabled. For running Fls in user mode the MCAL_ENABLE_USER_MODE_SUPPORT needs to be defined.
+    #endif
+#endif
+
+#define QSPI_PERFORM_DEVICE_CONFIG                      (STD_ON)
+
+
+/*==================================================================================================
+                                       DEFINES AND MACROS
+==================================================================================================*/
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* QSPI_IP_CFG_H */

s32/soc/s32z270/include/Qspi_Ip_CfgDefines.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QSPI_IP_CFG_DEFINES_H
+#define QSPI_IP_CFG_DEFINES_H
+
+/**
+*   @file Qspi_Ip_CfgDefines.h
+*
+*   @addtogroup IPV_QSPI
+*   Qspi_Ip_CfgDefines.h_Artifact
+*   @{
+*/
+
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define QSPI_IP_VENDOR_ID_CFG_DEFINES                    43
+#define QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG_DEFINES     4
+#define QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG_DEFINES     7
+#define QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG_DEFINES  0
+#define QSPI_IP_SW_MAJOR_VERSION_CFG_DEFINES             2
+#define QSPI_IP_SW_MINOR_VERSION_CFG_DEFINES             0
+#define QSPI_IP_SW_PATCH_VERSION_CFG_DEFINES             0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+
+/*==================================================================================================
+                                       DEFINES AND MACROS
+==================================================================================================*/
+
+
+#define QSPI_IP_SFP_ENABLE_GLOBAL                    (STD_ON)
+#define QSPI_IP_SFP_ENABLE_MDAD                      (STD_ON)
+#define QSPI_IP_SFP_ENABLE_FRAD                      (STD_ON)
+
+
+/* Enable Multicore support when using MemAcc*/
+#define QSPI_IP_MULTICORE_ENABLED                        (STD_OFF)
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* QSPI_IP_CFG_DEFINES_H */

s32/soc/s32z270/include/Qspi_Ip_Features.h

@@ -0,0 +1,114 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if !defined(QSPI_IP_FEATURES_H)
+#define QSPI_IP_FEATURES_H
+
+/**
+*   @file Qspi_Ip_Features.h
+*
+*   @addtogroup IPV_QSPI
+*   Qspi_Ip_Features.h_Artifact
+*   @{
+*/
+
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "S32Z2_QUADSPI.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define QSPI_IP_FEATURES_VENDOR_ID_CFG                      43
+#define QSPI_IP_FEATURES_AR_RELEASE_MAJOR_VERSION_CFG       4
+#define QSPI_IP_FEATURES_AR_RELEASE_MINOR_VERSION_CFG       7
+#define QSPI_IP_FEATURES_AR_RELEASE_REVISION_VERSION_CFG    0
+#define QSPI_IP_FEATURES_SW_MAJOR_VERSION_CFG               2
+#define QSPI_IP_FEATURES_SW_MINOR_VERSION_CFG               0
+#define QSPI_IP_FEATURES_SW_PATCH_VERSION_CFG               0
+
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/* QuadSPI module features */
+
+/*! @brief First address of the serial flash device on the AHB bus for QuadSPI instances */
+#define FEATURE_QSPI_AMBA_BASE                        {0x00000000UL,0x10000000UL}
+/*! @brief Size of AHB buffer. */
+#define FEATURE_QSPI_AHB_BUF_SIZE                     1024U
+/*! @brief Size of Tx FIFO. */
+#define FEATURE_QSPI_TX_BUF_SIZE                      1024U
+/*! @brief Size of Rx FIFO. */
+#define FEATURE_QSPI_RX_BUF_SIZE                      256U
+/*! @brief Number of LUT registers that make up a LUT sequence */
+#define FEATURE_QSPI_LUT_SEQUENCE_SIZE                5U
+/* Minimum entries of 4 bytes fill needed to allow Tx operation to start */
+#define FEATURE_QSPI_TX_MIN_BUF_FILL                  1U
+
+/*! @brief Supports Double Data Rate operation */
+#define FEATURE_QSPI_DDR                              1
+/*! @brief QSPI side B is available */
+#define FEATURE_QSPI_HAS_SIDE_B                       1
+/*! @brief Configurable Idle Signal Drive */
+#define FEATURE_QSPI_CONFIGURABLE_ISD                 1
+
+/*! @brief Supports addr. config options (column address, word addressable) */
+#define FEATURE_QSPI_ADDR_CFG                         1
+/*! @brief Supports byte swap */
+#define FEATURE_QSPI_BYTES_SWAP_ADDR                  1
+
+/*! @brief Supports center-aligned read strobe */
+#define FEATURE_QSPI_CENTER_ALIGNED_READ_STROBE       1
+/*! @brief Supports differential clock */
+#define FEATURE_QSPI_DIFFERENTIAL_CLOCK               1
+
+/*! @brief Supports internal DQS sampling mode */
+#define FEATURE_QSPI_INTERNAL_DQS                     0
+/*! @brief Supports loopback sampling mode */
+#define FEATURE_QSPI_LOOPBACK                         1
+/*! @brief Supports DQS loopback sampling mode */
+#define FEATURE_QSPI_LOOPBACK_DQS                     0
+/*! @brief Supports external DQS sampling mode */
+#define FEATURE_QSPI_EXTERNAL_DQS                     1
+/*! @brief Supports DQS_FA_SEL/DQS_FB_SEL field in MCR register for DQS selection */
+#define FEATURE_QSPI_SELECT_DQS                       1
+
+/*! @brief Supports Dll feature */
+#define FEATURE_QSPI_HAS_DLL                          1
+/*! @brief Supports full DLL features (as opposed to bypass mode only) */
+#define FEATURE_QSPI_EXTERNAL_DLL_FULL                1
+/*! @brief Supports DLL reference counter and DLL resolution */
+#define FEATURE_QSPI_DLL_LOOPCONTROL                  1
+
+/*! @brief Supports secure flash protection feature */
+#define FEATURE_QSPI_HAS_SFP                          1
+
+
+/*! @brief The maximum size of manufacturer & device ID that flash memories can have */
+#define FEATURE_EXFLS_FLASH_MDID_SIZE                  10U
+
+/*! @brief AHB base pointers initializer for all QSPI units */
+#define QuadSPI_AHB_PTRS                              FEATURE_QSPI_AMBA_BASE
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* QSPI_IP_FEATURES_H */