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s32: soc: s32z2: update QSPI clock sources
Select PERIPHPLL_DFS0 clock as QSPI0 clock source Select PERIPHPLL_DFS2 clock as QSPI1 clock source Update QSPI dividers so that value clocks: P4_QSPI0_1X_CLK is 200 MHz P4_QSPI0_2X_CLK is 400 MHz P4_QSPI1_1X_CLK is 150 MHz P4_QSPI1_2X_CLK is 300 MHz Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
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