Process completed with exit code 1.

See https://docs.zephyrproject.org/latest/contribute/guidelines.html#clang-format for more details. You may want to run clang-format on this change: -#define RADIO_CTRL_IRQn 21 /* Not provided by CMSIS; must be declared manually */ - -#define CLOCK_FREQ_64MHZ (64000000U) -#define CLOCK_FREQ_32MHZ (32000000U) -#define CLOCK_FREQ_16MHZ (16000000U) +#define RADIO_CTRL_IRQn 21 /* Not provided by CMSIS; must be declared manually */ + +#define CLOCK_FREQ_64MHZ (64000000U) +#define CLOCK_FREQ_32MHZ (32000000U) +#define CLOCK_FREQ_16MHZ (16000000U) /* Device tree node definitions */ -#define DT_RCC_SLOWCLK_NODE DT_PHANDLE(STM32_CLOCK_CONTROL_NODE, slow_clock) -#define DT_LSI_NODE DT_NODELABEL(clk_lsi) +#define DT_RCC_SLOWCLK_NODE DT_PHANDLE(STM32_CLOCK_CONTROL_NODE, slow_clock) +#define DT_LSI_NODE DT_NODELABEL(clk_lsi) /* Device tree properties definitions */ -#define STM32_WB0_CLKSYS_PRESCALER \ - DT_PROP(STM32_CLOCK_CONTROL_NODE, clksys_prescaler) +#define STM32_WB0_CLKSYS_PRESCALER DT_PROP(STM32_CLOCK_CONTROL_NODE, clksys_prescaler) #if DT_NODE_HAS_PROP(STM32_CLOCK_CONTROL_NODE, slow_clock) -# if !DT_NODE_HAS_STATUS(DT_RCC_SLOWCLK_NODE, okay) -# error slow-clock source is not enabled -# endif - -# if DT_SAME_NODE(DT_RCC_SLOWCLK_NODE, DT_LSI_NODE) -# define STM32_WB0_SLOWCLK_SRC LL_RCC_LSCO_CLKSOURCE_LSI -# elif DT_SAME_NODE(DT_RCC_SLOWCLK_NODE, DT_NODELABEL(clk_lse)) -# define STM32_WB0_SLOWCLK_SRC LL_RCC_LSCO_CLKSOURCE_LSE -# elif DT_SAME_NODE(DT_RCC_SLOWCLK_NODE, DT_NODELABEL(clk_16mhz_div512)) -# define STM32_WB0_SLOWCLK_SRC LL_RCC_LSCO_CLKSOURCE_HSI64M_DIV2048 -# else -# error Invalid device selected as slow-clock -# endif +#if !DT_NODE_HAS_STATUS(DT_RCC_SLOWCLK_NODE, okay) +#error slow-clock source is not enabled +#endif + +#if DT_SAME_NODE(DT_RCC_SLOWCLK_NODE, DT_LSI_NODE) +#define STM32_WB0_SLOWCLK_SRC LL_RCC_LSCO_CLKSOURCE_LSI +#elif DT_SAME_NODE(DT_RCC_SLOWCLK_NODE, DT_NODELABEL(clk_lse)) +#define STM32_WB0_SLOWCLK_SRC LL_RCC_LSCO_CLKSOURCE_LSE +#elif DT_SAME_NODE(DT_RCC_SLOWCLK_NODE, DT_NODELABEL(clk_16mhz_div512)) +#define STM32_WB0_SLOWCLK_SRC LL_RCC_LSCO_CLKSOURCE_HSI64M_DIV2048 +#else +#error Invalid device selected as slow-clock +#endif #endif /* DT_NODE_HAS_PROP(STM32_CLOCK_CONTROL_NODE, slow_clock) */ #if DT_NODE_HAS_PROP(DT_LSI_NODE, runtime_measurement_interval) - #define STM32_WB0_RUNTIME_LSI_CALIBRATION 1 - #define STM32_WB0_LSI_RUNTIME_CALIB_INTERVAL \ - DT_PROP(DT_LSI_NODE, runtime_measurement_interval) +#define STM32_WB0_RUNTIME_LSI_CALIBRATION 1 +#define STM32_WB0_LSI_RUNTIME_CALIB_INTERVAL DT_PROP(DT_LSI_NODE, runtime_measurement_interval) #endif /* DT_NODE_HAS_PROP(clk_lsi, runtime_calibration_settings) */ /* Verify device tree properties are correct */ BUILD_ASSERT(!IS_ENABLED(STM32_SYSCLK_SRC_HSE) || STM32_WB0_CLKSYS_PRESCALER != 64, - "clksys-prescaler cannot be 64 when SYSCLK source is Direct HSE"); + "clksys-prescaler cannot be 64 when SYSCLK source is Direct HSE"); #if defined(STM32_LSI_ENABLED) /* Check clock configuration allows MR_BLE IP to work. * This IP is required to perform LSI measurements. */ -# if defined(STM32_SYSCLK_SRC_HSI) - /* When using HSI without PLL, the "16MHz" output is not actually 16MHz, since - * the RC64M generator is imprecise. In this configuration, MR_BLE is broken. - * The CPU and MR_BLE must be running at 32MHz for MR_BLE to work with HSI. - */ - BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= CLOCK_FREQ_32MHZ, - "System clock frequency must be at least 32MHz to use LSI"); -# else - /* In PLL or Direct HSE mode, the clock is stable, so 16MHz can be used. */ - BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= CLOCK_FREQ_16MHZ, - "System clock frequency must be at least 16MHz to use LSI"); -# endif /* STM32_SYSCLK_SRC_HSI */ +#if defined(STM32_SYSCLK_SRC_HSI) +/* When using HSI without PLL, the "16MHz" output is not actually 16MHz, since + * the RC64M generator is imprecise. In this configuration, MR_BLE is broken. + * The CPU and MR_BLE must be running at 32MHz for MR_BLE to work wit

drivers/clock_control/clock_stm32_ll_wb0.c:84 -#define RADIO_CTRL_IRQn 21 /* Not provided by CMSIS; must be declared manually */ - -#define CLOCK_FREQ_64MHZ (64000000U) -#define CLOCK_FREQ_32MHZ (32000000U) -#define CLOCK_FREQ_16MHZ (16000000U) +#define RADIO_CTRL_IRQn 21 /* Not provided by CMSIS; must be declared manually */ + +#define CLOCK_FREQ_64MHZ (64000000U) +#define CLOCK_FREQ_32MHZ (32000000U) +#define CLOCK_FREQ_16MHZ (16000000U) /* Device tree node definitions */ -#define DT_RCC_SLOWCLK_NODE DT_PHANDLE(STM32_CLOCK_CONTROL_NODE, slow_clock) -#define DT_LSI_NODE DT_NODELABEL(clk_lsi) +#define DT_RCC_SLOWCLK_NODE DT_PHANDLE(STM32_CLOCK_CONTROL_NODE, slow_clock) +#define DT_LSI_NODE DT_NODELABEL(clk_lsi) /* Device tree properties definitions */ -#define STM32_WB0_CLKSYS_PRESCALER \ - DT_PROP(STM32_CLOCK_CONTROL_NODE, clksys_prescaler) +#define STM32_WB0_CLKSYS_PRESCALER DT_PROP(STM32_CLOCK_CONTROL_NODE, clksys_prescaler) #if DT_NODE_HAS_PROP(STM32_CLOCK_CONTROL_NODE, slow_clock) -# if !DT_NODE_HAS_STATUS(DT_RCC_SLOWCLK_NODE, okay) -# error slow-clock source is not enabled -# endif - -# if DT_SAME_NODE(DT_RCC_SLOWCLK_NODE, DT_LSI_NODE) -# define STM32_WB0_SLOWCLK_SRC LL_RCC_LSCO_CLKSOURCE_LSI -# elif DT_SAME_NODE(DT_RCC_SLOWCLK_NODE, DT_NODELABEL(clk_lse)) -# define STM32_WB0_SLOWCLK_SRC LL_RCC_LSCO_CLKSOURCE_LSE -# elif DT_SAME_NODE(DT_RCC_SLOWCLK_NODE, DT_NODELABEL(clk_16mhz_div512)) -# define STM32_WB0_SLOWCLK_SRC LL_RCC_LSCO_CLKSOURCE_HSI64M_DIV2048 -# else -# error Invalid device selected as slow-clock -# endif +#if !DT_NODE_HAS_STATUS(DT_RCC_SLOWCLK_NODE, okay) +#error slow-clock source is not enabled +#endif + +#if DT_SAME_NODE(DT_RCC_SLOWCLK_NODE, DT_LSI_NODE) +#define STM32_WB0_SLOWCLK_SRC LL_RCC_LSCO_CLKSOURCE_LSI +#elif DT_SAME_NODE(DT_RCC_SLOWCLK_NODE, DT_NODELABEL(clk_lse)) +#define STM32_WB0_SLOWCLK_SRC LL_RCC_LSCO_CLKSOURCE_LSE +#elif DT_SAME_NODE(DT_RCC_SLOWCLK_NODE, DT_NODELABEL(clk_16mhz_div512)) +#define STM32_WB0_SLOWCLK_SRC LL_RCC_LSCO_CLKSOURCE_HSI64M_DIV2048 +#else +#error Invalid device selected as slow-clock +#endif #endif /* DT_NODE_HAS_PROP(STM32_CLOCK_CONTROL_NODE, slow_clock) */ #if DT_NODE_HAS_PROP(DT_LSI_NODE, runtime_measurement_interval) - #define STM32_WB0_RUNTIME_LSI_CALIBRATION 1 - #define STM32_WB0_LSI_RUNTIME_CALIB_INTERVAL \ - DT_PROP(DT_LSI_NODE, runtime_measurement_interval) +#define STM32_WB0_RUNTIME_LSI_CALIBRATION 1 +#define STM32_WB0_LSI_RUNTIME_CALIB_INTERVAL DT_PROP(DT_LSI_NODE, runtime_measurement_interval) #endif /* DT_NODE_HAS_PROP(clk_lsi, runtime_calibration_settings) */ /* Verify device tree properties are correct */ BUILD_ASSERT(!IS_ENABLED(STM32_SYSCLK_SRC_HSE) || STM32_WB0_CLKSYS_PRESCALER != 64, - "clksys-prescaler cannot be 64 when SYSCLK source is Direct HSE"); + "clksys-prescaler cannot be 64 when SYSCLK source is Direct HSE"); #if defined(STM32_LSI_ENABLED) /* Check clock configuration allows MR_BLE IP to work. * This IP is required to perform LSI measurements. */ -# if defined(STM32_SYSCLK_SRC_HSI) - /* When using HSI without PLL, the "16MHz" output is not actually 16MHz, since - * the RC64M generator is imprecise. In this configuration, MR_BLE is broken. - * The CPU and MR_BLE must be running at 32MHz for MR_BLE to work with HSI. - */ - BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= CLOCK_FREQ_32MHZ, - "System clock frequency must be at least 32MHz to use LSI"); -# else - /* In PLL or Direct HSE mode, the clock is stable, so 16MHz can be used. */ - BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= CLOCK_FREQ_16MHZ, - "System clock frequency must be at least 16MHz to use LSI"); -# endif /* STM32_SYSCLK_SRC_HSI */ +#if defined(STM32_SYSCLK_SRC_HSI) +/* When using HSI without PLL, the "16MHz" output is not actually 16MHz, since + * the RC64M generator is imprecise. In this configuration, MR_BLE is broken. + * The CPU and MR_BLE must be running at 32MHz for MR_BLE to work with HSI. + */ +BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= CLOCK_FREQ_32MHZ, + "System clock f

drivers/clock_control/clock_stm32_ll_wb0.c:114 - (CONFIG_STM32WB0_LSI_MEASUREMENT_WINDOW - 1)); + (CONFIG_STM32WB0_LSI_MEASUREMENT_WINDOW - 1));

drivers/clock_control/clock_stm32_ll_wb0.c:175 - stm32wb0_lsi_frequency = - (CLOCK_FREQ_32MHZ / fast_clock_cycles_elapsed) - * CONFIG_STM32WB0_LSI_MEASUREMENT_WINDOW; + stm32wb0_lsi_frequency = (CLOCK_FREQ_32MHZ / fast_clock_cycles_elapsed) * + CONFIG_STM32WB0_LSI_MEASUREMENT_WINDOW;

drivers/clock_control/clock_stm32_ll_wb0.c:253 - clock_control_subsys_t sub_system, - void *data) + clock_control_subsys_t sub_system, void *data)

drivers/clock_control/clock_stm32_ll_wb0.c:276 -static inline int get_apb0_periph_clkrate(uint32_t enr, uint32_t *rate, - uint32_t slow_clock, uint32_t sysclk, uint32_t clk_sys) +static inline int get_apb0_periph_clkrate(uint32_t enr, uint32_t *rate, uint32_t slow_clock, + uint32_t sysclk, uint32_t clk_sys)

drivers/clock_control/clock_stm32_ll_wb0.c:285 - /* SYSCLK peripherals: all timers */ + /* SYSCLK peripherals: all timers */

drivers/clock_control/clock_stm32_ll_wb0.c:313 -static inline int get_apb1_periph_clkrate(uint32_t enr, uint32_t *rate, - uint32_t clk_sys) +static inline int get_apb1_periph_clkrate(uint32_t enr, uint32_t *rate, uint32_t clk_sys)

drivers/clock_control/clock_stm32_ll_wb0.c:363 - /* ADC has two enable bits - accept all combinations. */ + /* ADC has two enable bits - accept all combinations. */

drivers/clock_control/clock_stm32_ll_wb0.c:396 - clock_control_subsys_t sub_system, - uint32_t *rate) + clock_control_subsys_t sub_system, uint32_t *rate)