Add initial support for the Raspberry Pi Pico 2 #159924
ajf58compliance.yml
on: pull_request
Run compliance checks on patch series (PR)
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Run compliance checks on patch series (PR)
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Run compliance checks on patch series (PR):
ClangFormat.txt#L1
See https://docs.zephyrproject.org/latest/contribute/guidelines.html#clang-format for more details.
You may want to run clang-format on this change:
-#define AUXSRC_lposc LPOSC_CLKSRC
-#define AUXSRC_clk_hstx CLK_HSTX
-#define AUXSRC_otp_clk2fc OTP_CLK2FC
+#define AUXSRC_lposc LPOSC_CLKSRC
+#define AUXSRC_clk_hstx CLK_HSTX
+#define AUXSRC_otp_clk2fc OTP_CLK2FC
File:drivers/clock_control/clock_control_rpi_pico.c
Line:120
You may want to run clang-format on this change:
-#define AUXSTEM_clk_peri CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_
+#define AUXSTEM_clk_peri CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_
File:drivers/clock_control/clock_control_rpi_pico.c
Line:131
You may want to run clang-format on this change:
- rpi_pico_clkid_pll_sys,
- rpi_pico_clkid_gpin0,
- rpi_pico_clkid_gpin1,
- rpi_pico_clkid_pll_usb,
- rpi_pico_clkid_rosc_ph,
- rpi_pico_clkid_xosc,
- rpi_pico_clkid_clk_sys,
- rpi_pico_clkid_clk_usb,
- rpi_pico_clkid_clk_adc,
+ rpi_pico_clkid_pll_sys, rpi_pico_clkid_gpin0, rpi_pico_clkid_gpin1,
+ rpi_pico_clkid_pll_usb, rpi_pico_clkid_rosc_ph, rpi_pico_clkid_xosc,
+ rpi_pico_clkid_clk_sys, rpi_pico_clkid_clk_usb, rpi_pico_clkid_clk_adc,
File:drivers/clock_control/clock_control_rpi_pico.c
Line:325
You may want to run clang-format on this change:
- } else if (id == rpi_pico_clkid_clk_usb ||
- id == rpi_pico_clkid_clk_peri ||
+ } else if (id == rpi_pico_clkid_clk_usb || id == rpi_pico_clkid_clk_peri ||
id == rpi_pico_clkid_clk_adc ||
#if defined(RPI_PICO_CLKID_CLK_RTC)
id == rpi_pico_clkid_clk_rtc ||
#endif
- id == rpi_pico_clkid_clk_gpout0 ||
- id == rpi_pico_clkid_clk_gpout1 ||
- id == rpi_pico_clkid_clk_gpout2 ||
- id == rpi_pico_clkid_clk_gpout3) {
+ id == rpi_pico_clkid_clk_gpout0 || id == rpi_pico_clkid_clk_gpout1 ||
+ id == rpi_pico_clkid_clk_gpout2 || id == rpi_pico_clkid_clk_gpout3) {
File:drivers/clock_control/clock_control_rpi_pico.c
Line:454
You may want to run clang-format on this change:
- if (id == rpi_pico_clkid_clk_sys ||
- id == rpi_pico_clkid_clk_usb ||
+ if (id == rpi_pico_clkid_clk_sys || id == rpi_pico_clkid_clk_usb ||
id == rpi_pico_clkid_clk_adc ||
#if defined(RPI_PICO_CLKID_CLK_RTC)
id == rpi_pico_clkid_clk_rtc ||
#endif
- id == rpi_pico_clkid_clk_ref ||
- id == rpi_pico_clkid_clk_gpout0 ||
- id == rpi_pico_clkid_clk_gpout1 ||
- id == rpi_pico_clkid_clk_gpout2 ||
+ id == rpi_pico_clkid_clk_ref || id == rpi_pico_clkid_clk_gpout0 ||
+ id == rpi_pico_clkid_clk_gpout1 || id == rpi_pico_clkid_clk_gpout2 ||
File:drivers/clock_control/clock_control_rpi_pico.c
Line:504
You may want to run clang-format on this change:
- unreset_block_wait(RESETS_RESET_BITS &
- ~(RESETS_RESET_ADC_BITS |
+ unreset_block_wait(RESETS_RESET_BITS & ~(RESETS_RESET_ADC_BITS |
#if defined(RESETS_RESET_RTC_BITS)
- RESETS_RESET_RTC_BITS |
+ RESETS_RESET_RTC_BITS |
#endif
#if defined(RESETS_RESET_HSTX_BITS)
- RESETS_RESET_HSTX_BITS |
-#endif
- RESETS_RESET_SPI0_BITS | RESETS_RESET_SPI1_BITS |
- RESETS_RESET_UART0_BITS | RESETS_RESET_UART1_BITS |
- RESETS_RESET_USBCTRL_BITS));
+ RESETS_RESET_HSTX_BITS |
+#endif
+ RESETS_RESET_SPI0_BITS | RESETS_RESET_SPI1_BITS |
+ RESETS_RESET_UART0_BITS | RESETS_RESET_UART1_BITS |
+ RESETS_RESET_USBCTRL_BITS));
File:drivers/clock_control/clock_control_rpi_pico.c
Line:677
You may want to run clang-format on this change:
- .clocks_data = {
- [RPI_PICO_CLKID_CLK_GPOUT0] = {
- .source = 0,
- .aux_source = CLOCK_AUX_SOURCE(clk_gpout0),
- .source_rate = SRC_CLOCK_FREQ(clk_gpout0),
- .rate = CLOCK_FREQ(clk_gpout0),
+ .clocks_data =
+ {
+ [RPI_PICO_CLKID_CLK_GPOUT0] =
+ {
+ .source = 0,
+ .aux_source = CLOCK_AUX_SOURCE(clk_gpout0),
+ .source_rate = SRC_CLOCK_FREQ(clk_gpout0),
+ .rate = CLOCK_FREQ(clk_gpout0),
+ },
+ [RPI_PICO_CLKID_CLK_GPOUT1] =
+ {
+ .source = 0,
+ .aux_source = CLOCK_AUX_SOURCE(clk_gpout1),
+ .source
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You may want to run clang-format on this change:
drivers/clock_control/clock_control_rpi_pico.c#L120
drivers/clock_control/clock_control_rpi_pico.c:120
-#define AUXSRC_lposc LPOSC_CLKSRC
-#define AUXSRC_clk_hstx CLK_HSTX
-#define AUXSRC_otp_clk2fc OTP_CLK2FC
+#define AUXSRC_lposc LPOSC_CLKSRC
+#define AUXSRC_clk_hstx CLK_HSTX
+#define AUXSRC_otp_clk2fc OTP_CLK2FC
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You may want to run clang-format on this change:
drivers/clock_control/clock_control_rpi_pico.c#L131
drivers/clock_control/clock_control_rpi_pico.c:131
-#define AUXSTEM_clk_peri CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_
+#define AUXSTEM_clk_peri CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_
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You may want to run clang-format on this change:
drivers/clock_control/clock_control_rpi_pico.c#L325
drivers/clock_control/clock_control_rpi_pico.c:325
- rpi_pico_clkid_pll_sys,
- rpi_pico_clkid_gpin0,
- rpi_pico_clkid_gpin1,
- rpi_pico_clkid_pll_usb,
- rpi_pico_clkid_rosc_ph,
- rpi_pico_clkid_xosc,
- rpi_pico_clkid_clk_sys,
- rpi_pico_clkid_clk_usb,
- rpi_pico_clkid_clk_adc,
+ rpi_pico_clkid_pll_sys, rpi_pico_clkid_gpin0, rpi_pico_clkid_gpin1,
+ rpi_pico_clkid_pll_usb, rpi_pico_clkid_rosc_ph, rpi_pico_clkid_xosc,
+ rpi_pico_clkid_clk_sys, rpi_pico_clkid_clk_usb, rpi_pico_clkid_clk_adc,
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You may want to run clang-format on this change:
drivers/clock_control/clock_control_rpi_pico.c#L454
drivers/clock_control/clock_control_rpi_pico.c:454
- } else if (id == rpi_pico_clkid_clk_usb ||
- id == rpi_pico_clkid_clk_peri ||
+ } else if (id == rpi_pico_clkid_clk_usb || id == rpi_pico_clkid_clk_peri ||
id == rpi_pico_clkid_clk_adc ||
#if defined(RPI_PICO_CLKID_CLK_RTC)
id == rpi_pico_clkid_clk_rtc ||
#endif
- id == rpi_pico_clkid_clk_gpout0 ||
- id == rpi_pico_clkid_clk_gpout1 ||
- id == rpi_pico_clkid_clk_gpout2 ||
- id == rpi_pico_clkid_clk_gpout3) {
+ id == rpi_pico_clkid_clk_gpout0 || id == rpi_pico_clkid_clk_gpout1 ||
+ id == rpi_pico_clkid_clk_gpout2 || id == rpi_pico_clkid_clk_gpout3) {
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You may want to run clang-format on this change:
drivers/clock_control/clock_control_rpi_pico.c#L504
drivers/clock_control/clock_control_rpi_pico.c:504
- if (id == rpi_pico_clkid_clk_sys ||
- id == rpi_pico_clkid_clk_usb ||
+ if (id == rpi_pico_clkid_clk_sys || id == rpi_pico_clkid_clk_usb ||
id == rpi_pico_clkid_clk_adc ||
#if defined(RPI_PICO_CLKID_CLK_RTC)
id == rpi_pico_clkid_clk_rtc ||
#endif
- id == rpi_pico_clkid_clk_ref ||
- id == rpi_pico_clkid_clk_gpout0 ||
- id == rpi_pico_clkid_clk_gpout1 ||
- id == rpi_pico_clkid_clk_gpout2 ||
+ id == rpi_pico_clkid_clk_ref || id == rpi_pico_clkid_clk_gpout0 ||
+ id == rpi_pico_clkid_clk_gpout1 || id == rpi_pico_clkid_clk_gpout2 ||
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You may want to run clang-format on this change:
drivers/clock_control/clock_control_rpi_pico.c#L677
drivers/clock_control/clock_control_rpi_pico.c:677
- unreset_block_wait(RESETS_RESET_BITS &
- ~(RESETS_RESET_ADC_BITS |
+ unreset_block_wait(RESETS_RESET_BITS & ~(RESETS_RESET_ADC_BITS |
#if defined(RESETS_RESET_RTC_BITS)
- RESETS_RESET_RTC_BITS |
+ RESETS_RESET_RTC_BITS |
#endif
#if defined(RESETS_RESET_HSTX_BITS)
- RESETS_RESET_HSTX_BITS |
-#endif
- RESETS_RESET_SPI0_BITS | RESETS_RESET_SPI1_BITS |
- RESETS_RESET_UART0_BITS | RESETS_RESET_UART1_BITS |
- RESETS_RESET_USBCTRL_BITS));
+ RESETS_RESET_HSTX_BITS |
+#endif
+ RESETS_RESET_SPI0_BITS | RESETS_RESET_SPI1_BITS |
+ RESETS_RESET_UART0_BITS | RESETS_RESET_UART1_BITS |
+ RESETS_RESET_USBCTRL_BITS));
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You may want to run clang-format on this change:
drivers/clock_control/clock_control_rpi_pico.c#L965
drivers/clock_control/clock_control_rpi_pico.c:965
- .clocks_data = {
- [RPI_PICO_CLKID_CLK_GPOUT0] = {
- .source = 0,
- .aux_source = CLOCK_AUX_SOURCE(clk_gpout0),
- .source_rate = SRC_CLOCK_FREQ(clk_gpout0),
- .rate = CLOCK_FREQ(clk_gpout0),
+ .clocks_data =
+ {
+ [RPI_PICO_CLKID_CLK_GPOUT0] =
+ {
+ .source = 0,
+ .aux_source = CLOCK_AUX_SOURCE(clk_gpout0),
+ .source_rate = SRC_CLOCK_FREQ(clk_gpout0),
+ .rate = CLOCK_FREQ(clk_gpout0),
+ },
+ [RPI_PICO_CLKID_CLK_GPOUT1] =
+ {
+ .source = 0,
+ .aux_source = CLOCK_AUX_SOURCE(clk_gpout1),
+ .source_rate = SRC_CLOCK_FREQ(clk_gpout1),
+ .rate = CLOCK_FREQ(clk_gpout1),
+ },
+ [RPI_PICO_CLKID_CLK_GPOUT2] =
+ {
+ .source = 0,
+ .aux_source = CLOCK_AUX_SOURCE(clk_gpout2),
+ .source_rate = SRC_CLOCK_FREQ(clk_gpout2),
+ .rate = CLOCK_FREQ(clk_gpout2),
+ },
+ [RPI_PICO_CLKID_CLK_GPOUT3] =
+ {
+ .source = 0,
+ .aux_source = CLOCK_AUX_SOURCE(clk_gpout3),
+ .source_rate = SRC_CLOCK_FREQ(clk_gpout3),
+ .rate = CLOCK_FREQ(clk_gpout3),
+ },
+ [RPI_PICO_CLKID_CLK_REF] =
+ {
+#if CLK_SRC_IS(clk_ref, rosc_ph)
+ .source = CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH,
+ .aux_source = 0,
+#elif CLK_SRC_IS(clk_ref, xosc)
+ .source = CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC,
+ .aux_source = 0,
+#else
+ .source = CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX,
+#endif
+ .source_rate = SRC_CLOCK_FREQ(clk_ref),
+ .rate = CLOCK_FREQ(clk_ref),
+ },
+ [RPI_PICO_CLKID_CLK_SYS] =
+ {
+#if CLK_SRC_IS(clk_sys, clk_ref)
+ .source = CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF,
+ .aux_source = 0,
+#else
+ .source = CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
+ .aux_source = CLOCK_AUX_SOURCE(clk_sys),
+#endif
+ .source_rate = SRC_CLOCK_FREQ(clk_sys),
+ .rate = CLOCK_FREQ(clk_sys),
+ },
+ [RPI_PICO_CLKID_CLK_PERI] =
+ {
+ .source = 0,
+ .aux_source = CLOCK_AUX_SOURCE(clk_peri),
+ .source_rate = SRC_CLOCK_FREQ(clk_peri),
+ .rate = CLOCK_FREQ(clk_peri),
+ },
+ [RPI_PICO_CLKID_CLK_USB] =
+ {
+ .source = 0,
+ .aux_source = CLOCK_AUX_SOURCE(clk_usb),
+ .source_rate = SRC_CLOCK_FREQ(clk_usb),
+ .rate = CLOCK_FREQ(clk_usb),
+ },
+ [RPI_PICO_CLKID_CLK_ADC] =
+ {
+ .source = 0,
+ .aux_source = CLOCK_AUX_SOURCE(clk_adc),
+ .source_rate = SRC_CLOCK_FREQ(clk_adc),
+ .rate = CLOCK_FREQ(clk_adc),
+ },
+#if defined(RPI_PICO_CLKID_CLK_RTC)
+ [RPI_PICO_CLKID_CLK_RTC] =
+ {
+ .source = 0,
+ .aux_source = CLOCK_AUX_SOURCE(clk_rtc),
+ .source_rate = SRC_CLOCK_FREQ(clk_rtc),
+ .rate = CLOCK_FREQ(clk_rtc),
+ },
+#elif defined(RPI_PICO_CLKID_CLK_HSTX)
+ [RPI_PICO_CLKID_CLK_HSTX] =
+ {
+ .source = 0,
+ .aux_source = CLOCK_AUX_SOURCE(clk_hstx),
+ .source_rate = SRC_CLOCK_FREQ(clk_hstx),
+ .rate = CLOCK_FREQ(clk_hstx),
+ },
+#endif
},
- [RPI_PICO_CLKID_CLK_GPOUT1] = {
- .source = 0,
- .aux_source = CLOCK_AUX_SOURCE(clk_gpout1),
- .source_rate = SRC_CLOCK_FREQ(clk_gpout1),
- .rate = CLOCK_FREQ(clk_gpout1),
+ .plls_data =
+ {
+ [RPI_PICO_PLL_SYS] =
+ {
+ .ref_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys),
+ clock_div),
+ .fb_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys),
+ fb_div),
+ .post_div1 = DT_PROP(
+ DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), post_div1),
+ .post_div2 = DT_PROP(
+ DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_sys), post_div2),
+ },
+ [RPI_PICO_PLL_USB] =
+ {
+ .ref_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb),
+ clock_div),
+ .fb_div = DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb),
+ fb_div),
+ .post_div1 = DT_PROP(
+ DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), post_div1),
+ .post_div2 = DT_PROP(
+ DT_INST_CLOCKS_CTLR_BY_NAME(0, pll_usb), post_div2),
+ },
},
- [RPI_PICO_CLKID_CLK_GPOUT2] = {
- .source = 0,
- .aux_source = CLOCK_AUX_SOURCE(clk_gpout2),
- .source_rate = SRC_CLOCK_FREQ(clk_g
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You may want to run clang-format on this change:
drivers/hwinfo/hwinfo_rpi_pico.c#L27
drivers/hwinfo/hwinfo_rpi_pico.c:27
-#define HAD_RUN_BIT BIT(POWMAN_CHIP_RESET_HAD_RUN_LOW_LSB)
+#define HAD_RUN_BIT BIT(POWMAN_CHIP_RESET_HAD_RUN_LOW_LSB)
#define HAD_PSM_RESTART_BIT BIT(POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_LSB)
-#define HAD_POR_BIT BIT(POWMAN_CHIP_RESET_HAD_POR_LSB)
+#define HAD_POR_BIT BIT(POWMAN_CHIP_RESET_HAD_POR_LSB)
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You may want to run clang-format on this change:
include/zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h#L14
include/zephyr/dt-bindings/clock/rpi_pico_rp2040_clock.h:14
-#define RPI_PICO_CLKID_CLK_USB 7
-#define RPI_PICO_CLKID_CLK_ADC 8
-#define RPI_PICO_CLKID_CLK_RTC 9
+#define RPI_PICO_CLKID_CLK_USB 7
+#define RPI_PICO_CLKID_CLK_ADC 8
+#define RPI_PICO_CLKID_CLK_RTC 9
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You may want to run clang-format on this change:
include/zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h#L14
include/zephyr/dt-bindings/clock/rpi_pico_rp2350_clock.h:14
-#define RPI_PICO_CLKID_CLK_HSTX 7
-#define RPI_PICO_CLKID_CLK_USB 8
-#define RPI_PICO_CLKID_CLK_ADC 9
+#define RPI_PICO_CLKID_CLK_HSTX 7
+#define RPI_PICO_CLKID_CLK_USB 8
+#define RPI_PICO_CLKID_CLK_ADC 9
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Artifacts
Produced during runtime
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compliance.xml
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3.75 KB |
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