Tsi m85 v1 (#2)

* TSI: board name changed

-ek_tsi to tsi board name changed
-comilance erros removed from some files

Signed-off-by: Ganesh Kethamalla <gkethamallax@tsavoritesi.com>

* TSI Board: compliance errors removed and and board variant name changed

-board variant name changed to m85 to cortex-m85
-white spaces and extra lines removed

Signed-off-by: Ganesh Kethamalla <gkethamallax@tsavoritesi.com>

* TSI Board: old board file removed from directory

-created tsi new directory, instead of using ek_tsi. that's removed old one.

Signed-off-by: Ganesh Kethamalla <gkethamallax@tsavoritesi.com>

* added new cpu configuration adsp

* Modified TXE address for DV environment testing

* @FIR-13: Create a new target "west build -p always -b tsi/skyp/txe samples/hello_world/"
and remove the old target "west build -p always -b tsi/mimx8ml8/adsp samples/hello_world/"
there are still references to using mimx8m tool chain and drivers but we will revisit
these later, I tried to make the change but gave up as it requires defining all of SOC
structure will rely on Ganesh to address these items.

* @FIR-13: Fix the lint and compliance warnings

* @FIR-13: Fixed compliance warning

* @FIR-13: Added tsi - Tsavorite Scalable Intelligence as a vendor

* @FIR-13: Fixed the sorting issue of vendors list

* removed unused symbol BOARD_TSI_MIMX8ML8_ADSP

* Synced for new target tsi/skyp/m85 that removed the ek_ prefix

* Removed white-spaces in main.c and Readme.rst

* renamed folder boards/tsi/tsi to boards/tsi/skyp

* Removed compilance check warnings

---------

Signed-off-by: Ganesh Kethamalla <gkethamallax@tsavoritesi.com>
Co-authored-by: Dinesh Reddy <dreddy@ws03.tsavoritesi.net>
Co-authored-by: Ashish Trivedi <atrivedi@tsavoritesi.com>
Co-authored-by: Meera Mankali <mmankali@wssim0.tsavoritesi.net>

boards/tsi/ek_tsi/Kconfig → boards/tsi/skyp/Kconfig

@@ -1,5 +1,5 @@
 # Copyright (c) 2024 TSI
 # SPDX-License-Identifier: Apache-2.0
 
-config BOARD_EK_TSI
- select QEMU_TARGET
+# config BOARD_TSI
+#  select QEMU_TARGET

boards/tsi/ek_tsi/Kconfig.defconfig → boards/tsi/skyp/Kconfig.defconfig

@@ -1,7 +1,7 @@
 # Copyright (c) 2024 TSI
 # SPDX-License-Identifier: Apache-2.0
 
-if BOARD_EK_TSI
+if BOARD_TSI
 
 # MPU-based null-pointer dereferencing detection cannot
 # be applied as the (0x0 - 0x400) is unmapped but QEMU

boards/tsi/skyp/Kconfig.tsi

@@ -0,0 +1,7 @@
+# Copyright (c) 2024 TSI
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_TSI
+ select SOC_PART_NUMBER_MIMX8ML8DVNLZ
+ select SOC_SKYP_M85 if BOARD_TSI_SKYP_M85
+ select SOC_MIMX8ML8_ADSP if BOARD_TSI_SKYP_TXE

boards/tsi/skyp/board.yml

@@ -0,0 +1,10 @@
+board:
+ name: tsi
+ vendor: tsi
+ socs:
+ - name: skyp
+ variants:
+ - name: tensilica
+ cpucluster: txe
+ - name: cortex-m85
+ cpucluster: m85

boards/tsi/ek_tsi/ek_tsi_skyp_m85-common.dtsi → boards/tsi/skyp/tsi_skyp_m85-common.dtsi

@@ -18,4 +18,3 @@ uart0: uart@14001000 {
  clocks = <&sysclk>;
  current-speed = <115200>;
 };
-

boards/tsi/ek_tsi/ek_tsi_skyp_m85.dts → boards/tsi/skyp/tsi_skyp_m85.dts

@@ -19,22 +19,16 @@
 
  chosen {
  zephyr,console = &jtag_uart;
- /*
- zephyr,console = &uart0;
- */
  zephyr,shell-uart = &jtag_uart;
- /*
- zephyr,shell-uart = &uart0;
- */
  zephyr,sram = &sram;
  zephyr,flash = &sram0;
  };
 
- jtag_uart: uart@95003000 {
- compatible = "altr,jtag-uart";
- reg = <0x95003000 0x8>;
- status = "enabled";
- };
+ jtag_uart: uart@95003000 {
+ compatible = "altr,jtag-uart";
+ reg = <0x95003000 0x8>;
+ status = "enabled";
+ };
 
  cpus {
  #address-cells = <1>;
@@ -57,11 +51,11 @@
  /* We utilize the secure addresses, if you subtract 0x10000000
  * you'll get the non-secure alias
  */
- itcm: itcm@4000 { /* alias @ 0x4000 */
- compatible = "zephyr,memory-region";
- reg = <0x4000 DT_SIZE_K(16)>;
- zephyr,memory-region = "ITCM";
- };
+ itcm: itcm@4000 { /* alias @ 0x4000 */
+ compatible = "zephyr,memory-region";
+ reg = <0x4000 DT_SIZE_K(16)>;
+ zephyr,memory-region = "ITCM";
+ };
 
  sram0: sram0@60000000 { /* alias @ 0x60000000 */
  compatible = "zephyr,memory-region";
@@ -91,14 +85,7 @@
  ddr4: memory@60700000 {
  device_type = "memory";
  compatible = "zephyr,memory-region";
- reg = <0x60700000 DT_SIZE_M(1)
- /*0x70000000 DT_SIZE_M(256)
- 0x80000000 DT_SIZE_M(256)
- 0x90000000 DT_SIZE_M(256)
- 0xa0000000 DT_SIZE_M(256)
- 0xb0000000 DT_SIZE_M(256)
- 0xc0000000 DT_SIZE_M(256)
- 0xd0000000 DT_SIZE_M(256)*/>;
+ reg = <0x60700000 DT_SIZE_M(1)>;
  zephyr,memory-region = "DDR4";
  };
 
@@ -108,7 +95,7 @@
  #size-cells = <1>;
  ranges = <0x0 0x81000000 0x1effffff>;
 
- #include "ek_tsi_skyp_m85-common.dtsi"
+ #include "tsi_skyp_m85-common.dtsi"
  };
  };
 };

boards/tsi/ek_tsi/ek_tsi_skyp_m85.yaml → boards/tsi/skyp/tsi_skyp_m85.yaml

@@ -1,4 +1,4 @@
-identifier: ek_tsi/skyp/m85
+identifier: tsi/skyp/m85
 name: TSI sky-p
 type: mcu
 arch: arm

boards/tsi/skyp/tsi_skyp_txe.dts

@@ -0,0 +1,47 @@
+/*
+ * Copyright 2021, 2023, 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_imx8m.dtsi>
+#include <nxp/nxp_imx/mimx8ml8dvnlz-pinctrl.dtsi>
+
+/ {
+ model = "NXP i.MX 8MPLUS Audio DSP";
+ compatible = "nxp";
+
+ chosen {
+ //zephyr,sram = &sram0;
+ zephyr,sram = &sram_txe;
+
+ zephyr,console = &uart4;
+ zephyr,shell-uart = &uart4;
+ };
+ sram_txe: memory@60040000 {
+ device_type = "memory";
+ compatible = "mmio-sram";
+ reg = <0x60040000 DT_SIZE_K(512)>;
+ };
+};
+
+&pinctrl {
+ uart4_default: uart4_default {
+ group0 {
+ pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>,
+ <&iomuxc_uart4_txd_uart_tx_uart4_tx>;
+ bias-pull-up;
+ slew-rate = "slow";
+ drive-strength = "x1";
+ };
+ };
+};
+
+&uart4 {
+ status = "okay";
+ current-speed = <115200>;
+ pinctrl-0 = <&uart4_default>;
+ pinctrl-names = "default";
+};

boards/tsi/skyp/tsi_skyp_txe.yaml

@@ -0,0 +1,16 @@
+identifier: tsi/skyp/txe
+name: TSI DSP
+type: mcu
+arch: xtensa
+toolchain:
+ - xcc
+ - xt-clang
+ - zephyr
+supported:
+ - uart
+testing:
+ ignore_tags:
+ - net
+ - bluetooth
+ - mcumgr
+vendor: nxp

boards/tsi/skyp/tsi_skyp_txe_defconfig

@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# size of stack for initialization and main thread
+CONFIG_MAIN_STACK_SIZE=3072
+
+# enable logger
+CONFIG_LOG=y
+
+# no need for a "raw" binary zephyr/zephyr.bin in the build directory
+CONFIG_BUILD_OUTPUT_BIN=y
+CONFIG_BUILD_OUTPUT_HEX=y
+
+# enable uart driver
+CONFIG_SERIAL=y
+
+# clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# console (remote proc console by default)
+CONFIG_CONSOLE=y
+
+# uart console (overrides remote proc console)
+CONFIG_UART_CONSOLE=y
+
+# enable pin controller
+CONFIG_PINCTRL=y

dts/bindings/vendor-prefixes.txt

@@ -683,6 +683,7 @@ tronfy Tronfy
 tronsmart Tronsmart
 truly Truly Semiconductors Limited
 tsd Theobroma Systems Design und Consulting GmbH
+tsi Tsavorite Scalable Intelligence
 tyan Tyan Computer Corporation
 u-blox u-blox
 u-boot U-Boot bootloader

soc/nxp/imx/imx8m/adsp/memory.h

@@ -14,14 +14,21 @@
 
 #define IRAM_RESERVE_HEADER_SPACE 0x400
 
-#define IRAM_BASE 0x3B6F8000
+/*#define IRAM_BASE 0x3B6F8000*/
+#define IRAM_BASE 0x60600000
+#define IRAM_SIZE 0x800
+
 #define IRAM_SIZE 0x800
 
-#define SDRAM0_BASE 0x92400000
-#define SDRAM0_SIZE 0x800000
+/*#define SDRAM0_BASE 0x92400000*/
+/*#define SDRAM0_SIZE 0x800000*/
+#define SDRAM0_BASE 0x60601000
+#define SDRAM0_SIZE 0xFF000
 
-#define SDRAM1_BASE 0x92C00000
-#define SDRAM1_SIZE 0x800000
+/*#define SDRAM1_BASE 0x92C00000*/
+/*#define SDRAM1_SIZE 0x800000*/
+#define SDRAM1_BASE 0x60700000
+#define SDRAM1_SIZE 0x100000
 
 /* The reset vector address in SRAM and its size */
 #define MEM_RESET_TEXT_SIZE 0x2E0
@@ -36,7 +43,8 @@
 /*
  * EXCEPTIONS and VECTORS
  */
-#define XCHAL_RESET_VECTOR0_PADDR_IRAM 0x3B6F8000
+/*#define XCHAL_RESET_VECTOR0_PADDR_IRAM 0x3B6F8000*/
+#define XCHAL_RESET_VECTOR0_PADDR_IRAM 0x6060000
 
 /* Vector and literal sizes */
 #define MEM_VECT_LIT_SIZE 0x4
@@ -78,20 +86,27 @@
 #define IDT_SIZE 0x2000
 
 /* physical DSP addresses */
-#define IRAM_BASE 0x3B6F8000
+/*#define IRAM_BASE 0x3B6F8000*/
+#define IRAM_BASE 0x60600000
 #define IRAM_SIZE 0x800
 
-#define DRAM0_BASE 0x3B6E8000
-#define DRAM0_SIZE 0x8000
+/*#define DRAM0_BASE 0x3B6E8000*/
+#define DRAM0_BASE 0x70800000
+#define DRAM0_SIZE 0x8000
 
-#define DRAM1_BASE 0x3B6F0000
-#define DRAM1_SIZE 0x8000
+/*#define DRAM1_BASE 0x3B6F0000*/
+#define DRAM1_BASE 0x80608000
+#define DRAM1_SIZE 0x8000
 
-#define SDRAM0_BASE 0x92400000
-#define SDRAM0_SIZE 0x800000
+/*#define SDRAM0_BASE 0x92400000*/
+#define SDRAM0_BASE 0x60601000
+/*#define SDRAM0_SIZE 0x800000*/
+#define SDRAM0_SIZE 0xFF000
 
-#define SDRAM1_BASE 0x92C00000
-#define SDRAM1_SIZE 0x800000
+/*#define SDRAM1_BASE 0x92C00000*/
+#define SDRAM1_BASE 0x60700000
+/*#define SDRAM1_SIZE 0x800000*/
+#define SDRAM1_SIZE 0x100000
 
 #define XSHAL_MU2_SIDEB_BYPASS_PADDR 0x30E70000
 #define MU_BASE XSHAL_MU2_SIDEB_BYPASS_PADDR

soc/tsi/skyp_v1/Kconfig

@@ -13,7 +13,6 @@ config SOC_SERIES_SKYP_V1
  select ARMV8_1_M_MVEI
  select ARMV8_1_M_MVEF
  select ARMV8_1_M_PMU
-
 
 config ARMV8_1_M_PMU_EVENTCNT
  int

soc/tsi/skyp_v1/Kconfig.defconfig

@@ -8,5 +8,5 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 
 config NUM_IRQS
  default 128
- 
+
 endif # SOC_SERIES_SKYP_V1

soc/tsi/skyp_v1/Kconfig.soc

@@ -18,7 +18,7 @@ config SOC_SKYP_M85
  bool
  select SOC_SKYP
  help
- skyp_m85 
+ skyp_m85
 
 config SOC_SERIES
  default "skyp_v1" if SOC_SERIES_SKYP_V1

soc/tsi/soc.yml

@@ -5,4 +5,5 @@ family:
  socs:
  - name: skyp
  cpuclusters:
- - name: m85
+ - name: m85
+ - name: txe

tsi_app/m85/CMakeLists.txt

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(m85)
+
+target_sources(app PRIVATE src/main.c)

tsi_app/m85/README.rst

@@ -0,0 +1,30 @@
+.. _m85:
+
+TSI Banner
+###########
+
+Overview
+********
+
+This is the core TSI M85 Zephyr platform application startup code. It prints TSI Banner to the console, enables logging functionality so that developers can log messages to console at different levels of severity such as Info, Warning, Error & Debug. It also enables the shell functionality.
+
+Building and Running
+********************
+
+This application can be built as follows:
+
+.. zephyr-app-commands::
+ :zephyr-app: tsi_m85
+ :host-os: unix
+ :board: tsi/skyp/m85
+ :goals: run
+ :compact:
+
+
+Output
+=============
+
+.. code-block:: console
+***** !! WELCOME TO TSAVORITE SCALABLE INTELLIGENCE !! *****
+[00:00:00.010,000] <inf> tsi_m85: Test Platform: tsi/skyp/m85
+[00:00:00.020,000] <wrn> tsi_m85: Testing on FPGA; Multi module init TBD

tsi_app/m85/overlay_deferred.conf

@@ -0,0 +1,9 @@
+CONFIG_LOG_MODE_IMMEDIATE=n
+CONFIG_LOG_MODE_DEFERRED=y
+CONFIG_LOG_BUFFER_SIZE=1024
+CONFIG_LOG_PROCESS_THREAD=y
+CONFIG_LOG_PROCESS_THREAD_SLEEP_MS=100
+CONFIG_LOG_PROCESS_TRIGGER_THRESHOLD=2
+CONFIG_LOG_PROCESS_THREAD_STACK_SIZE=4096
+CONFIG_LOG_BLOCK_IN_THREAD=y
+CONFIG_LOG_BACKEND_UART=y

tsi_app/m85/overlay_immediate.conf

@@ -0,0 +1 @@
+CONFIG_LOG_BACKEND_UART=y