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drivers: i3c: cadence: fix tx_fifo width for target mode on rev_id 1p7
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Cadence I3C target FIFO width has been increased to 4 bytes in i3c
hardware rev_id 1p7. Writing 1 byte to 4 byte FIFOs can cause
unintentional padding for bytes written from TX threshold interrupt
handler. Fixed the target callback to handle tx width of i3c target
writes to FIFO, by using run time rev_id check.

Signed-off-by: Naveen Gangadharan <naveeng1001@meta.com>
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naveeng1001 committed Sep 17, 2024
1 parent 48a077f commit 2144341
Showing 1 changed file with 100 additions and 39 deletions.
139 changes: 100 additions & 39 deletions drivers/i3c/i3c_cdns.c
Original file line number Diff line number Diff line change
Expand Up @@ -2387,6 +2387,104 @@ static void cdns_i3c_target_ibi_hj_complete(const struct device *dev)
}
#endif

static void cdns_i3c_slv_sdr_tx_th_int_handler(const struct device *dev,
const struct i3c_target_callbacks *target_cb)
{
int status = 0;
struct cdns_i3c_data *data = dev->data;
const struct cdns_i3c_config *config = dev->config;

if (target_cb != NULL && target_cb->read_processed_cb) {
/* while tx fifo is not full and there is still data available */
while ((!(sys_read32(config->base + SLV_STATUS1) &
SLV_STATUS1_SDR_TX_FULL)) && (status == 0)) {
/* call function pointer for read */
/* with rev 1p7, as a target, the fifos are full word,
* otherwise only the first byte is used
*/
if (REV_ID_REV(data->hw_cfg.rev_id) >= REV_ID_VERSION(1, 7)) {
uint32_t tx_data = 0;
bool data_valid = false;

for (int j = 0; j < 4; j++) {
uint8_t byte;
/* will return negative if no data left to transmit and 0
* if data available
*/
status = target_cb->read_processed_cb(data->target_config,
&byte);
if (status == 0) {
data_valid = true;
tx_data |= (byte << (j * 8));
}
}
if (data_valid) {
cdns_i3c_write_tx_fifo(config, &tx_data, sizeof(uint32_t));
}
} else {
uint8_t byte;
/* will return negative if no data left to transmit and 0 if
* data available
*/
status = target_cb->read_processed_cb(data->target_config,
&byte);
if (status == 0) {
cdns_i3c_write_tx_fifo(config, &byte, sizeof(uint8_t));
}
}
}
}
}

static void cdns_i3c_slv_ddr_tx_th_int_handler(const struct device *dev,
const struct i3c_target_callbacks *target_cb)
{
int status = 0;
struct cdns_i3c_data *data = dev->data;
const struct cdns_i3c_config *config = dev->config;

if (target_cb != NULL && target_cb->read_processed_cb) {
while ((!(sys_read32(config->base + SLV_STATUS1) &
SLV_STATUS1_DDR_TX_FULL)) && (status == 0)) {
/* call function pointer for read */
/* with rev 1p7, as a target, the fifos are full word,
* otherwise only the first byte is used
*/
if (REV_ID_REV(data->hw_cfg.rev_id) >= REV_ID_VERSION(1, 7)) {
uint32_t tx_data = 0;
bool data_valid = false;

for (int j = 0; j < 4; j++) {
uint8_t byte;
/* will return negative if no data left to transmit and 0
* if data available
*/
status = target_cb->read_processed_cb(data->target_config,
&byte);
if (status == 0) {
data_valid = true;
tx_data |= (byte << (j * 8));
}
}
if (data_valid) {
cdns_i3c_write_ddr_tx_fifo(config, &tx_data,
sizeof(uint32_t));
}
} else {
uint8_t byte;
/* will return negative if no data left to transmit and 0 if
* data available
*/
status = target_cb->read_processed_cb(data->target_config,
&byte);
if (status == 0) {
cdns_i3c_write_ddr_tx_fifo(config, &byte, sizeof(byte));
}
}
}
}
}

static void cdns_i3c_irq_handler(const struct device *dev)
{
const struct cdns_i3c_config *config = dev->config;
Expand Down Expand Up @@ -2468,25 +2566,7 @@ static void cdns_i3c_irq_handler(const struct device *dev)

/* SLV SDR tx fifo threshold */
if (int_sl & SLV_INT_SDR_TX_THR) {
int status = 0;

if (target_cb != NULL && target_cb->read_processed_cb) {
/* while tx fifo is not full and there is still data available */
while ((!(sys_read32(config->base + SLV_STATUS1) &
SLV_STATUS1_SDR_TX_FULL)) &&
(status == 0)) {
/* call function pointer for read */
uint8_t byte;
/* will return negative if no data left to transmit and 0 if
* data available
*/
status = target_cb->read_processed_cb(data->target_config,
&byte);
if (status == 0) {
cdns_i3c_write_tx_fifo(config, &byte, sizeof(byte));
}
}
}
cdns_i3c_slv_sdr_tx_th_int_handler(dev, target_cb);
}

/* SLV SDR rx complete */
Expand Down Expand Up @@ -2619,26 +2699,7 @@ static void cdns_i3c_irq_handler(const struct device *dev)

/*SLV DDR TX THR*/
if (int_sl & SLV_INT_DDR_TX_THR) {
int status = 0;

if (target_cb != NULL && target_cb->read_processed_cb) {

while ((!(sys_read32(config->base + SLV_STATUS1) &
SLV_STATUS1_DDR_TX_FULL)) &&
(status == 0)) {
/* call function pointer for read */
uint8_t byte;
/* will return negative if no data left to transmit
* and 0 if data available
*/
status = target_cb->read_processed_cb(data->target_config,
&byte);
if (status == 0) {
cdns_i3c_write_ddr_tx_fifo(config, &byte,
sizeof(byte));
}
}
}
cdns_i3c_slv_ddr_tx_th_int_handler(dev, target_cb);
}
}
}
Expand Down

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