shields: Add support for M5Stack-Core2 base shield.

M5Stack-Core2 comes with a base shield that is connected to the M5Stack extention connector. It features a MPU6886 6-axis motion tracker and a SPM1423 microphone. Signed-off-by: Martin Kiepfer <m.kiepfer@teleschirm.org>
zephyrproject-rtos · Sep 14, 2023 · 2d0ab8c · 2d0ab8c
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diff --git a/boards/shields/m5stack_core2_ext/Kconfig.defconfig b/boards/shields/m5stack_core2_ext/Kconfig.defconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2023 Martin Kiepfer <mrmarteng@teleschirm.org>
+# SPDX-License-Identifier: Apache-2.0
+
+if M5STACK_CORE2_EXT
+
+config SENSOR
+	default y
+
+endif # M5STACK_CORE2_EXT
diff --git a/boards/shields/m5stack_core2_ext/Kconfig.shield b/boards/shields/m5stack_core2_ext/Kconfig.shield
@@ -0,0 +1,5 @@
+# Copyright (c) 2023 Martin Kiepfer <mrmarteng@teleschirm.org>
+# SPDX-License-Identifier: Apache-2.0
+
+config M5STACK_CORE2_EXT
+	def_bool $(shields_list_contains,m5stack_core2_ext)
diff --git a/boards/shields/m5stack_core2_ext/doc/img/m5stack_core2_ext.webp b/boards/shields/m5stack_core2_ext/doc/img/m5stack_core2_ext.webp
diff --git a/boards/shields/m5stack_core2_ext/doc/index.rst b/boards/shields/m5stack_core2_ext/doc/index.rst
@@ -0,0 +1,49 @@
+.. _m5stack_core2_ext:
+
+M5Stack-Core2 base shield
+####################################
+
+Overview
+********
+
+M5Stack-Core2 comes with a base shield that is connected to the M5Stack
+extension connector. It features a MPU6886 6-axis motion tracker and a SPM1423
+microphone.
+
+.. figure:: img/m5stack_core2_ext.webp
+        :align: center
+        :alt: M5Stack-Core2-EXT
+        :width: 400 px
+
+        M5Stack-Core2-Extension module
+
+Pins Assignments
+================
+
++----------------------+--------------+
+| Shield Connector Pin | Function     |
++======================+==============+
+| 16                   | I2C - intSDA |
++----------------------+--------------+
+| 17                   | I2C - intSCL |
++----------------------+--------------+
+
+Programming
+***********
+
+Set ``-DSHIELD=m5stack_core2_ext`` when you invoke ``west build``.
+For example:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/drivers/mpu6050
+   :board: m5stack_core2
+   :shield: m5stack_core2_ext
+   :goals: build
+
+References
+**********
+
+.. target-notes::
+
+.. _datasheet:
+   https://docs.m5stack.com/en/core/core2
diff --git a/boards/shields/m5stack_core2_ext/m5stack_core2_ext.overlay b/boards/shields/m5stack_core2_ext/m5stack_core2_ext.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2023 Martin Kiepfer <mrmarteng@teleschirm.org>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&m5stack_mbus_i2c0 {
+	status = "okay";
+
+	mbus_mpu6886: mbus_mpu6886@68 {
+		status = "okay";
+		compatible = "invensense,mpu6050";
+		reg = <0x68>;
+	};
+};
+
+/ {
+
+};
diff --git a/boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi b/boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi
@@ -24,6 +24,14 @@
 		pinmux = <UART1_RX_GPIO33>;
 	};
 
+	uart2_rx_gpio13: uart2_rx_gpio13 {
+		pinmux = <UART2_RX_GPIO13>;
+	};
+
+	uart2_tx_gpio14: uart2_rx_gpio14 {
+		pinmux = <UART2_TX_GPIO14>;
+	};
+
 	uart1_tx_gpio32: uart1_tx_gpio32 {
 		pinmux = <UART1_TX_GPIO32>;
 	};

diff --git a/boards/xtensa/m5stack_core2/m5stack_core2.dts b/boards/xtensa/m5stack_core2/m5stack_core2.dts
@@ -8,6 +8,7 @@
 #include <espressif/esp32/esp32_d0wd_v3.dtsi>
 #include "m5stack_core2-pinctrl.dtsi"
 #include "grove_connectors.dtsi"
+#include "m5stack_mbus_connectors.dtsi"
 #include <zephyr/dt-bindings/display/ili9xxx.h>
 #include <zephyr/dt-bindings/regulator/axp192.h>
 

diff --git a/boards/xtensa/m5stack_core2/m5stack_mbus_connectors.dtsi b/boards/xtensa/m5stack_core2/m5stack_mbus_connectors.dtsi
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2023 Martin Kiepfer
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	m5stack_mbus_header: m5stack_mbus_connector {
+		compatible = "m5stack,mbus-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = /* 0 GND */
+			   <1 0 &gpio1 4 0>,	/* ADC0 */
+			   /* 2 GND */
+			   <3 0 &gpio1 5 0>,	/* ADC1 */
+			   /* 4  GND */
+			   /* 5 RESET */
+			   <6 0 &gpio0 23 0>,	/* MOSI */
+			   <7 0 &gpio0 25 0>,	/* DAC0 */
+			   <8 0 &gpio1 7 0>,	/* MISO */
+			   <9 0 &gpio0 26 0>,	/* DAC1 */
+			   <10 0 &gpio0 18 0>,	/* SCK */
+			   /* 11 3.3V */
+			   <12 0 &gpio0 3 0>,	/* RXD0 */
+			   <13 0 &gpio0 1 0>,	/* TXD0 */
+			   <14 0 &gpio0 13 0>,	/* RXD1 */
+			   <15 0 &gpio0 14 0>,	/* TXD1 */
+			   <16 0 &gpio0 21 0>,	/* intSDA */
+			   <17 0 &gpio0 22 0>,	/* intSCL */
+			   <18 0 &gpio1 0 0>,	/* SDA */
+			   <19 0 &gpio1 1 0>,	/* SCL */
+			   <20 0 &gpio0 27 0>,	/* GPIO */
+			   <21 0 &gpio0 19 0>,	/* I2S_WS */
+			   <22 0 &gpio0 2 0>,	/* I2S_OUT */
+			   <23 0 &gpio0 0 0>,	/* I2S_MCLK */
+			   /* 24 NC */
+			   <25 0 &gpio1 3 0>;	/* I2S_EN */
+			   /* 26 NC */
+			   /* 27 5V */
+			   /* 28 NC */
+			   /* 29 BAT */
+	};
+};
+
+m5stack_mbus_i2c0: &i2c0 {};
+m5stack_mbus_i2c1: &i2c1 {};
+m5stack_mbus_uart0: &uart1 {};
+m5stack_mbus_uart1: &uart2 {};
+m5stack_mbus_spi: &spi3 {};