soc: esp32: rework soc and dts structure

Apply to ESP32, ESP32S2, ESP32S3. Signed-off-by: Marek Matej <marek.matej@espressif.com>
zephyrproject-rtos · May 30, 2023 · 390f93d · 390f93d
1 parent 147d406
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diff --git a/boards/xtensa/esp32/esp32.dts b/boards/xtensa/esp32/esp32.dts
@@ -5,7 +5,7 @@
  */
 /dts-v1/;
 
-#include <espressif/esp32.dtsi>
+#include <espressif/esp32wroom.dtsi>
 #include "esp32-pinctrl.dtsi"
 
 / {

diff --git a/dts/xtensa/espressif/esp32.dtsi b/dts/xtensa/espressif/esp32.dtsi
@@ -113,7 +113,7 @@
 
 			flash0: flash@0 {
 				compatible = "soc-nv-flash";
-				reg = <0 0x400000>;
+/*				reg = <0 0x400000>;  */
 				erase-block-size = <4096>;
 				write-block-size = <4>;
 			};

diff --git a/dts/xtensa/espressif/esp32d0wd.dtsi b/dts/xtensa/espressif/esp32d0wd.dtsi
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32.dtsi"
+
+/* placeholder - this is part used in SiP modules
+ * and on some boards - flash/psram size needs to
+ * be specified on board level
+ */
diff --git a/dts/xtensa/espressif/esp32d0wdr2.dtsi b/dts/xtensa/espressif/esp32d0wdr2.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32.dtsi"
diff --git a/dts/xtensa/espressif/esp32d2wd.dtsi b/dts/xtensa/espressif/esp32d2wd.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32.dtsi"
+
+&flash0 {
+    reg = <0x00000000 DT_SIZE_M(2)>;
+};
diff --git a/dts/xtensa/espressif/esp32pico.dtsi b/dts/xtensa/espressif/esp32pico.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32.dtsi"
+
+&flash0 {
+    reg = <0x00000000 DT_SIZE_M(4)>;
+};
diff --git a/dts/xtensa/espressif/esp32pico02.dtsi b/dts/xtensa/espressif/esp32pico02.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32.dtsi"
+
+&flash0 {
+    reg = <0x0 DT_SIZE_M(8)>;
+};
diff --git a/dts/xtensa/espressif/esp32picod4.dtsi b/dts/xtensa/espressif/esp32picod4.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32.dtsi"
+
+&flash0 {
+    reg = <0x0 DT_SIZE_M(4)>;
+};
diff --git a/dts/xtensa/espressif/esp32u4wdh.dtsi b/dts/xtensa/espressif/esp32u4wdh.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32.dtsi"
+
+&flash0 {
+    reg = <0x0 DT_SIZE_M(4)>;
+};
diff --git a/dts/xtensa/espressif/esp32wroom.dtsi b/dts/xtensa/espressif/esp32wroom.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32.dtsi"
+
+&flash0 {
+    reg = <0x0 DT_SIZE_M(4)>;
+};
diff --git a/dts/xtensa/espressif/esp32wrover.dtsi b/dts/xtensa/espressif/esp32wrover.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp32.dtsi"
+
+&flash0 {
+    reg = <0x0 DT_SIZE_M(4)>;
+};
diff --git a/soc/riscv/espressif_esp32/CMakeLists.txt b/soc/riscv/espressif_esp32/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})
+#add_subdirectory(common)
+#zephyr_include_directories(common)
diff --git a/soc/riscv/espressif_esp32/Kconfig b/soc/riscv/espressif_esp32/Kconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2023 Espressif
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_ESP32
+        bool
+
+if SOC_FAMILY_ESP32
+
+config SOC_FAMILY
+        string
+        default "espressif_esp32"
+
+source "soc/riscv/espressif_esp32/*/Kconfig.soc"
+
+endif # SOC_FAMILY_ESP32
+
diff --git a/soc/riscv/espressif_esp32/Kconfig.defconfig b/soc/riscv/espressif_esp32/Kconfig.defconfig
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/arm/st_stm32/*/Kconfig.defconfig.series"
diff --git a/soc/riscv/espressif_esp32/Kconfig.soc b/soc/riscv/espressif_esp32/Kconfig.soc
@@ -0,0 +1,6 @@
+# ST Microelectronics STM32 MCU line
+
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/arm/st_stm32/*/Kconfig.series"
diff --git a/soc/riscv/esp32c3/CMakeLists.txt → ...cv/espressif_esp32/esp32c3/CMakeLists.txt b/soc/riscv/esp32c3/CMakeLists.txt → ...cv/espressif_esp32/esp32c3/CMakeLists.txt
diff --git a/soc/riscv/esp32c3/Kconfig.defconfig → ...espressif_esp32/esp32c3/Kconfig.defconfig b/soc/riscv/esp32c3/Kconfig.defconfig → ...espressif_esp32/esp32c3/Kconfig.defconfig
diff --git a/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series b/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series
@@ -0,0 +1,50 @@
+# Copyright (c) 2021 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_NXP_IMX8
+
+config SOC_SERIES
+	string
+	default "imx8"
+
+config SOC_TOOLCHAIN_NAME
+	string
+	default "nxp_imx_adsp"
+
+config SOC
+	string
+	default "nxp_imx8"
+
+config SMP
+	default n
+
+config XTENSA_TIMER
+	default y
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 666000000 if XTENSA_TIMER
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 50000
+
+config KERNEL_ENTRY
+	default "__start"
+
+config MULTI_LEVEL_INTERRUPTS
+	default n
+
+config 2ND_LEVEL_INTERRUPTS
+	default n
+
+config DYNAMIC_INTERRUPTS
+	default y
+
+config LOG
+	default y
+
+# To prevent test uses TEST_LOGGING_MINIMAL
+config TEST_LOGGING_DEFAULTS
+	default n
+	depends on TEST
+
+endif # SOC_SERIES_NXP_IMX8
diff --git a/soc/riscv/espressif_esp32/esp32c3/Kconfig.series b/soc/riscv/espressif_esp32/esp32c3/Kconfig.series
@@ -0,0 +1,13 @@
+# Copyright (c) 2021 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NXP_IMX8
+	bool "NXP i.MX8"
+	select SOC_FAMILY_NXP_ADSP
+	select XTENSA
+	select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
+	select XTENSA_RESET_VECTOR
+	select XTENSA_USE_CORE_CRT1
+	select ATOMIC_OPERATIONS_BUILTIN
+	help
+	  NXP i.MX8
diff --git a/soc/riscv/esp32c3/Kconfig.soc → ...riscv/espressif_esp32/esp32c3/Kconfig.soc b/soc/riscv/esp32c3/Kconfig.soc → ...riscv/espressif_esp32/esp32c3/Kconfig.soc
diff --git a/soc/riscv/esp32c3/default.ld → soc/riscv/espressif_esp32/esp32c3/default.ld b/soc/riscv/esp32c3/default.ld → soc/riscv/espressif_esp32/esp32c3/default.ld
diff --git a/soc/riscv/esp32c3/idle.c → soc/riscv/espressif_esp32/esp32c3/idle.c b/soc/riscv/esp32c3/idle.c → soc/riscv/espressif_esp32/esp32c3/idle.c
diff --git a/soc/riscv/esp32c3/linker.ld → soc/riscv/espressif_esp32/esp32c3/linker.ld b/soc/riscv/esp32c3/linker.ld → soc/riscv/espressif_esp32/esp32c3/linker.ld
diff --git a/soc/riscv/esp32c3/loader.c → soc/riscv/espressif_esp32/esp32c3/loader.c b/soc/riscv/esp32c3/loader.c → soc/riscv/espressif_esp32/esp32c3/loader.c
diff --git a/soc/riscv/esp32c3/mcuboot.ld → soc/riscv/espressif_esp32/esp32c3/mcuboot.ld b/soc/riscv/esp32c3/mcuboot.ld → soc/riscv/espressif_esp32/esp32c3/mcuboot.ld
diff --git a/soc/riscv/esp32c3/pinctrl_soc.h → ...scv/espressif_esp32/esp32c3/pinctrl_soc.h b/soc/riscv/esp32c3/pinctrl_soc.h → ...scv/espressif_esp32/esp32c3/pinctrl_soc.h
diff --git a/soc/riscv/esp32c3/power.c → soc/riscv/espressif_esp32/esp32c3/power.c b/soc/riscv/esp32c3/power.c → soc/riscv/espressif_esp32/esp32c3/power.c
diff --git a/soc/riscv/esp32c3/soc.c → soc/riscv/espressif_esp32/esp32c3/soc.c b/soc/riscv/esp32c3/soc.c → soc/riscv/espressif_esp32/esp32c3/soc.c
diff --git a/soc/riscv/esp32c3/soc.h → soc/riscv/espressif_esp32/esp32c3/soc.h b/soc/riscv/esp32c3/soc.h → soc/riscv/espressif_esp32/esp32c3/soc.h
diff --git a/soc/riscv/esp32c3/soc_irq.S → soc/riscv/espressif_esp32/esp32c3/soc_irq.S b/soc/riscv/esp32c3/soc_irq.S → soc/riscv/espressif_esp32/esp32c3/soc_irq.S
diff --git a/soc/riscv/esp32c3/soc_irq.c → soc/riscv/espressif_esp32/esp32c3/soc_irq.c b/soc/riscv/esp32c3/soc_irq.c → soc/riscv/espressif_esp32/esp32c3/soc_irq.c
diff --git a/soc/riscv/esp32c3/vectors.S → soc/riscv/espressif_esp32/esp32c3/vectors.S b/soc/riscv/esp32c3/vectors.S → soc/riscv/espressif_esp32/esp32c3/vectors.S
diff --git a/soc/xtensa/esp32/Kconfig.defconfig b/soc/xtensa/esp32/Kconfig.defconfig
diff --git a/soc/xtensa/espressif_esp32/CMakeLists.txt b/soc/xtensa/espressif_esp32/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})
+add_subdirectory(common)
diff --git a/soc/xtensa/espressif_esp32/Kconfig b/soc/xtensa/espressif_esp32/Kconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_ESP32
+	bool
+
+if SOC_FAMILY_ESP32
+
+config SOC_FAMILY
+	string
+	default "espressif_esp32"
+
+source "soc/xtensa/espressif_esp32/*/Kconfig.soc"
+
+endif # SOC_FAMILY_ESP32
diff --git a/soc/xtensa/espressif_esp32/Kconfig.defconfig b/soc/xtensa/espressif_esp32/Kconfig.defconfig
@@ -0,0 +1,4 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/xtensa/espressif_esp32/*/Kconfig.defconfig.series"
diff --git a/soc/xtensa/espressif_esp32/Kconfig.soc b/soc/xtensa/espressif_esp32/Kconfig.soc
@@ -0,0 +1,4 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/xtensa/espressif_esp32/*/Kconfig.series"
diff --git a/soc/xtensa/espressif_esp32/common/CMakeLists.txt b/soc/xtensa/espressif_esp32/common/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+#zephyr_sources(stm32cube_hal.c)
+#zephyr_linker_sources_ifdef(CONFIG_STM32_CCM SECTIONS ccm.ld)
+#zephyr_linker_sources_ifdef(CONFIG_STM32_BACKUP_SRAM SECTIONS stm32_backup_sram.ld)
+#zephyr_sources_ifdef(CONFIG_STM32_BACKUP_SRAM stm32_backup_sram.c)
+#zephyr_sources(soc_config.c)
diff --git a/soc/xtensa/esp32/CMakeLists.txt → ...ensa/espressif_esp32/esp32/CMakeLists.txt b/soc/xtensa/esp32/CMakeLists.txt → ...ensa/espressif_esp32/esp32/CMakeLists.txt
@@ -40,7 +40,7 @@ if(CONFIG_BOOTLOADER_ESP_IDF)
     ${CMAKE_COMMAND} -G${CMAKE_GENERATOR}
     -S ${espidf_components_dir}/bootloader/subproject
     -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig
-    -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC}
+    -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES}
     -DPYTHON_DEPS_CHECKED=1
     -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER}
     -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER}

diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32d0wd b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32d0wd
@@ -0,0 +1,16 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+#ESP32-D0WD-V3
+#flash 0
+#psram 0
+#gpio 34
+#used_gpio 6,7,8,9,10,11
+#cert BT_SIG
+
+if SOC_ESP32D0WD
+
+config SOC
+	default "esp32d0wd"
+
+endif # SOC_ESP32D0WD config
diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32d0wdr2 b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32d0wdr2
@@ -0,0 +1,37 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+#ESP32-D0WDR2
+#flash 0
+#psram 2
+#gpio 34
+#used_gpio 6,7,8,9,10,11
+
+if SOC_ESP32D0WDR2
+
+config SOC
+	default "esp32d0wdr2"
+
+#config ESP_SPIRAM
+#	default y
+#
+#config SPIRAM_TYPE_ESPPSRAM16
+#	default y
+#
+#config D0WD_PSRAM_CLK_IO
+#	int "PSRAM CLK IO number"
+#	range 0 33
+#	default 17
+#	help
+#	  The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
+#	  1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
+#
+#config D0WD_PSRAM_CS_IO
+#	int "PSRAM CS IO number"
+#	range 0 33
+#	default 16
+#	help
+#	  The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
+#	  1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
+
+endif # SOC_ESP32D0WDR2 config