soc: add OpenHW Group CVA6 SoC

Adds support for the CVA6 family of RISC-V CPUs.
CVA6 is commonly found as a soft core CPU on FPGA designs.
Different configurations and instruction set extensions can be
configured, and different SoCs targeting various FPGA boards are
available.
This commit adds support for the 32-bit and 64-bit configurations
of CVA6, as well as three slightly different SoCs (a minimal 32-bit
configuration, a 64-bit configuration without FPU, a 64-bit
configuration with FPU).
The commit also adds several configurations of CVA6 for different
boards, such as the Genesys II, the Arty and the CVA6 testbench
environment.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>

boards/openhwgroup/cv32a6_arty_a7_100/Kconfig.cv32a6_arty_a7_100

@@ -0,0 +1,5 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+config BOARD_CV32A6_ARTY_A7_100
+	select SOC_CV32A6
+	select SOC_FAMILY_CVA6_PROVIDE_FPGA_POWEROFF

boards/openhwgroup/cv32a6_arty_a7_100/board.cmake

@@ -0,0 +1,8 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg")
+board_runner_args(openocd "--use-elf")
+board_runner_args(openocd "--verify")
+board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x8f000000 -work-area-size 16780000")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/openhwgroup/cv32a6_arty_a7_100/board.yml

@@ -0,0 +1,7 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board:
+  name: cv32a6_arty_a7_100
+  vendor: openhwgroup
+  socs:
+    - name: cv32a6

boards/openhwgroup/cv32a6_arty_a7_100/cv32a6_arty_a7_100.dts

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <openhwgroup/cv32a6.dtsi>
+
+/ {
+	model = "Openhardwaregroup CV32A6 on Arty A7 100";
+	compatible = "ariane,cv32a6_arty_a7_100";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &memory0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+	clock-frequency = <25000000>;
+
+	current-speed = <57600>;
+
+	// different interrupt than the CISPA version of the SoC
+	interrupts = <1 4>;
+};
+
+&spi0 {
+	status = "okay";
+	// different interrupt than the CISPA version of the SoC
+	interrupts = <2 2>;
+};
+
+&clint{
+	status = "okay";
+};
+
+&dma0 {
+	status = "disabled";
+};
+
+
+&mdio0{
+	status = "disabled";
+};
+
+&eth0 {
+	status = "disabled";
+};
+
+// Arty only has 256 MiB of memory
+&memory0 {
+	reg = <0x80000000 0x10000000>;
+};
+
+// Arty can only run at 25 Mhz
+&cpus_0 {
+	timebase-frequency = <12500000>;
+};
+
+&cpu_0 {
+	clock-frequency = <25000000>;
+};
+

boards/openhwgroup/cv32a6_arty_a7_100/cv32a6_arty_a7_100_defconfig

@@ -0,0 +1,42 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+CONFIG_BASE64=y
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
+CONFIG_CONSOLE_HANDLER=y
+CONFIG_XIP=n
+CONFIG_INIT_STACKS=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
+CONFIG_POWEROFF=y
+
+# RNG
+CONFIG_TIMER_RANDOM_GENERATOR=y
+CONFIG_TEST_RANDOM_GENERATOR=y
+
+# IRQs
+CONFIG_MULTI_LEVEL_INTERRUPTS=y
+CONFIG_2ND_LEVEL_INTERRUPTS=y
+# 1 PLIC
+CONFIG_NUM_2ND_LEVEL_AGGREGATORS=1
+CONFIG_PLIC=y
+CONFIG_3RD_LEVEL_INTERRUPTS=n
+
+# no networking support on this board
+
+# logging
+CONFIG_LOG=y
+CONFIG_LOG_DEFAULT_LEVEL=3
+CONFIG_THREAD_NAME=y
+
+# increased stack sizes
+CONFIG_ISR_STACK_SIZE=524288
+CONFIG_MAIN_STACK_SIZE=524288
+CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=524288
+CONFIG_IDLE_STACK_SIZE=524288
+
+# slower clock on Arty
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12500000

boards/openhwgroup/cv32a6_arty_a7_100/support/ariane.cfg

@@ -0,0 +1,44 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+# Based on the ariane.cfg from the cva6 project:
+# https://github.com/openhwgroup/cva6/blob/master/corev_apu/fpga/ariane_arty_a7.cfg
+adapter driver ftdi
+
+transport select jtag
+
+ftdi vid_pid 0x0403 0x6010
+
+# Channel 1 is UART
+ftdi channel 0
+
+# https://github.com/epsilon537/boxlambda/blob/master/scripts/arty_a7_100t.openocd.cfg
+ftdi layout_init 0x00e8 0x60eb
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id 0x13631093
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
+
+riscv set_ir idcode 0x09
+riscv set_ir dtmcs 0x22
+riscv set_ir dmi 0x23
+
+riscv set_command_timeout_sec 120
+
+adapter speed  100
+
+# prefer to use sba for system bus access
+riscv set_mem_access progbuf sysbus abstract
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Try enabling address translation (only works for newer versions)
+if { [catch {riscv set_enable_virtual on} ] } {
+    echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." }
+
+init
+halt
+echo "Ready for Remote Connections"

boards/openhwgroup/cv32a6_genesysII/Kconfig.cv32a6_genesysII

@@ -0,0 +1,5 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+config BOARD_CV32A6_GENESYSII
+	select SOC_CV32A6
+	select SOC_FAMILY_CVA6_PROVIDE_FPGA_POWEROFF

boards/openhwgroup/cv32a6_genesysII/board.cmake

@@ -0,0 +1,8 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg")
+board_runner_args(openocd "--use-elf")
+board_runner_args(openocd "--verify")
+board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x90000000 -work-area-size 16780000")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/openhwgroup/cv32a6_genesysII/board.yml

@@ -0,0 +1,7 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board:
+  name: cv32a6_genesysII
+  vendor: openhwgroup
+  socs:
+    - name: cv32a6

boards/openhwgroup/cv32a6_genesysII/cv32a6_genesysII.dts

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <openhwgroup/cv32a6.dtsi>
+
+/ {
+	model = "Openhardwaregroup CV32A6 on Genesys II";
+	compatible = "ariane,cv32a6_genesysII";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &memory0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+	// different interrupt than the CISPA version of the SoC
+	interrupts = <1 4>;
+};
+
+&spi0 {
+	status = "okay";
+	// different interrupt than the CISPA version of the SoC
+	interrupts = <2 2>;
+};
+
+&clint{
+	status = "okay";
+};
+
+&dma0 {
+	status = "disabled";
+};
+
+
+&mdio0{
+	status = "disabled";
+};
+
+&eth0 {
+	status = "disabled";
+};
+
+&eth {
+	status = "okay";
+};
+
+&xlnx_gpio {
+	status = "okay";
+};
+
+

boards/openhwgroup/cv32a6_genesysII/cv32a6_genesysII_defconfig

@@ -0,0 +1,40 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+CONFIG_BASE64=y
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
+CONFIG_CONSOLE_HANDLER=y
+CONFIG_XIP=n
+CONFIG_INIT_STACKS=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=25000000
+CONFIG_FPU=y
+CONFIG_POWEROFF=y
+
+# RNG
+CONFIG_TIMER_RANDOM_GENERATOR=y
+CONFIG_TEST_RANDOM_GENERATOR=y
+
+# IRQs
+CONFIG_MULTI_LEVEL_INTERRUPTS=y
+CONFIG_2ND_LEVEL_INTERRUPTS=y
+# 1 PLIC
+CONFIG_NUM_2ND_LEVEL_AGGREGATORS=1
+CONFIG_PLIC=y
+CONFIG_3RD_LEVEL_INTERRUPTS=n
+
+# no networking support on this board
+
+# logging
+CONFIG_LOG=y
+CONFIG_LOG_DEFAULT_LEVEL=3
+CONFIG_THREAD_NAME=y
+
+# increased stack sizes
+CONFIG_ISR_STACK_SIZE=524288
+CONFIG_MAIN_STACK_SIZE=524288
+CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=524288
+CONFIG_IDLE_STACK_SIZE=524288

boards/openhwgroup/cv32a6_genesysII/support/ariane.cfg

@@ -0,0 +1,49 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+# Based on the ariane.cfg from the cva6 project:
+# https://github.com/openhwgroup/cva6/blob/master/corev_apu/fpga/ariane.cfg
+adapter_khz     1000
+
+interface ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+# Channel 1 is taken by Xilinx JTAG
+ftdi_channel 0
+
+# links:
+# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
+#
+# Bit  MPSSE     FT2232    JTAG    Type   Description
+# Bit0 TCK       ADBUS0    TCK     Out    Clock Signal Output
+# Bit1 TDI       ADBUS1    TDI     Out    Serial Data Out
+# Bit2 TDO       ADBUS2    TDO     In     Serial Data In
+# Bit3 TMS       ADBUS3    TMS     Out    Select Signal Out
+# Bit4 GPIOL0    ADBUS4    nTRST   In/Out General Purpose I/O
+# this corresponds to the following in/out layout, with TMS initially set to 1
+ftdi_layout_init 0x0018 0x001b
+# we only have to specify nTRST, the others are assigned correctly by default
+ftdi_layout_signal nTRST -ndata 0x0010
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+riscv set_reset_timeout_sec 120
+riscv set_command_timeout_sec 120
+
+# prefer to use sba for system bus access
+riscv set_prefer_sba off
+
+# Try enabling address translation (only works for newer versions)
+if { [catch {riscv set_enable_virtual on} ] } {
+    echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." }
+
+init
+halt
+echo "Ready for Remote Connections"

boards/openhwgroup/cv64a6_arty_a7_100/Kconfig.cv64a6_arty_a7_100

@@ -0,0 +1,5 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+config BOARD_CV64A6_ARTY_A7_100
+	select SOC_CV64A6_IMAC
+	select SOC_FAMILY_CVA6_PROVIDE_FPGA_POWEROFF

boards/openhwgroup/cv64a6_arty_a7_100/board.cmake

@@ -0,0 +1,8 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg")
+board_runner_args(openocd "--use-elf")
+board_runner_args(openocd "--verify")
+board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x8f000000 -work-area-size 16780000")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/openhwgroup/cv64a6_arty_a7_100/board.yml

@@ -0,0 +1,7 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board:
+  name: cv64a6_arty_a7_100
+  vendor: openhwgroup
+  socs:
+    - name: cv64a6