arch/arm: Use TPIDRURO on cortex-a too

V7-A also supports TPIDRURO, so go ahead and use that for TLS, enabling
thread local storage for the other ARM architectures.

Add __aeabi_read_tp function in case code was compiled to use that.

Signed-off-by: Keith Packard <keithp@keithp.com>

arch/Kconfig

@@ -33,7 +33,7 @@ config ARM
 	# FIXME: current state of the code for all ARM requires this, but
 	# is really only necessary for Cortex-M with ARM MPU!
 	select GEN_PRIV_STACKS
-	select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_CORTEX_R || CPU_CORTEX_M
+	select ARCH_HAS_THREAD_LOCAL_STORAGE
 	help
 	  ARM architecture
 

arch/arm/core/aarch32/cortex_a_r/CMakeLists.txt

@@ -15,3 +15,4 @@ zephyr_library_sources(
   )
 
 zephyr_library_sources_ifdef(CONFIG_USERSPACE thread.c)
+zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE __aeabi_read_tp.S)

arch/arm/core/aarch32/cortex_a_r/__aeabi_read_tp.S

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2020 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <toolchain.h>
+
+_ASM_FILE_PROLOGUE
+
+GTEXT(__aeabi_read_tp)
+
+GDATA(z_arm_tls_ptr)
+
+SECTION_FUNC(text, __aeabi_read_tp)
+	mrc 15, 0, r0, c13, c0, 3
+	bx lr

arch/arm/core/aarch32/swap_helper.S

@@ -184,7 +184,7 @@ out_fp_endif:
     adds r4, r2, r4
     ldr r0, [r4]
 
-#if defined(CONFIG_CPU_CORTEX_R)
+#if defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_CORTEX_A)
     /* Store TLS pointer in the "Process ID" register.
      * This register is used as a base pointer to all
      * thread variables with offsets added by toolchain.