drivers: clock_control: rp2350: DO NOT MERGE Unwedge clock_control fo…

…r RP2350

This breaks support for RP2040 in the interest of performing bringup of
the RP2350 SoC and the Raspberry Pi Pico 2 board. This needs fixing
before merging onto main.

Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>

drivers/clock_control/clock_control_rpi_pico.c

@@ -102,7 +102,9 @@
 #define AUXSRC_clk_sys CLK_SYS
 #define AUXSRC_clk_usb CLK_USB
 #define AUXSRC_clk_adc CLK_ADC
+#if defined(CONFIG_SOC_SERIES_RP20XX)
 #define AUXSRC_clk_rtc CLK_RTC
+#endif
 #define AUXSRC_clk_gpin0 CLKSRC_GPIN0
 #define AUXSRC_clk_gpin1 CLKSRC_GPIN1
 
@@ -114,7 +116,9 @@
 #define AUXSTEM_clk_sys CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_
 #define AUXSTEM_clk_usb CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_
 #define AUXSTEM_clk_adc CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_
+#if defined(CONFIG_SOC_SERIES_RP20XX)
 #define AUXSTEM_clk_rtc CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_
+#endif
 #define AUXSTEM_clk_peri CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_
 
 #define TUPLE_ENTRY(n, p, i) \
@@ -223,9 +227,11 @@ uint64_t rpi_pico_frequency_count(const struct device *dev, clock_control_subsys
  case rpi_pico_clkid_clk_adc:
  fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_ADC;
  break;
+#if defined(SOC_RP2040)
  case rpi_pico_clkid_clk_rtc:
  fc0_id = CLOCKS_FC0_SRC_VALUE_CLK_RTC;
  break;
+#endif
  case rpi_pico_clkid_pll_sys:
  fc0_id = CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY;
  break;
@@ -611,14 +617,17 @@ static int clock_control_rpi_pico_init(const struct device *dev)
  RESETS_RESET_PLL_USB_BITS | RESETS_RESET_SYSCFG_BITS |
  RESETS_RESET_PLL_SYS_BITS));
 
- unreset_block_wait(RESETS_RESET_BITS &
- ~(RESETS_RESET_ADC_BITS | RESETS_RESET_RTC_BITS |
+ unreset_block(RESETS_RESET_BITS &
+ ~(RESETS_RESET_ADC_BITS |
+#if defined(SOC_RP2040)
+ RESETS_RESET_RTC_BITS |
+#endif
  RESETS_RESET_SPI0_BITS | RESETS_RESET_SPI1_BITS |
  RESETS_RESET_UART0_BITS | RESETS_RESET_UART1_BITS |
  RESETS_RESET_USBCTRL_BITS | RESETS_RESET_PWM_BITS));
 
  /* Start tick in watchdog */
- watchdog_hw->tick = ((CLOCK_FREQ_xosc/1000000) | WATCHDOG_TICK_ENABLE_BITS);
+ watchdog_start_tick(CLOCK_FREQ_xosc / 1000000);
 
  clocks_regs->resus.ctrl = 0;
 
@@ -704,7 +713,7 @@ static int clock_control_rpi_pico_init(const struct device *dev)
  return ret;
  }
 
- unreset_block_wait(RESETS_RESET_BITS);
+ unreset_block(RESETS_RESET_BITS);
 
  if (IS_ENABLED(CONFIG_RPI_PICO_ROSC_USE_MEASURED_FREQ)) {
  data->rosc_freq =
@@ -756,8 +765,10 @@ BUILD_ASSERT(SRC_CLOCK_FREQ(clk_usb) >= CLOCK_FREQ_clk_usb,
  "clk_usb: clock divider is out of range");
 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_adc) >= CLOCK_FREQ_clk_adc,
  "clk_adc: clock divider is out of range");
+#if defined(CONFIG_SOC_SERIES_RP20XX)
 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_rtc) >= CLOCK_FREQ_clk_rtc,
  "clk_rtc: clock divider is out of range");
+#endif
 BUILD_ASSERT(SRC_CLOCK_FREQ(clk_peri) >= CLOCK_FREQ_clk_peri,
  "clk_peri: clock divider is out of range");
 
@@ -839,12 +850,14 @@ static const struct clock_control_rpi_pico_config clock_control_rpi_pico_config
  .source_rate = SRC_CLOCK_FREQ(clk_adc),
  .rate = CLOCK_FREQ(clk_adc),
  },
+#if defined(CONFIG_SOC_SERIES_RP20XX)
  [RPI_PICO_CLKID_CLK_RTC] = {
  .source = 0,
  .aux_source = CLOCK_AUX_SOURCE(clk_rtc),
  .source_rate = SRC_CLOCK_FREQ(clk_rtc),
  .rate = CLOCK_FREQ(clk_rtc),
  },
+#endif
  },
  .plls_data = {
  [RPI_PICO_PLL_SYS] = {

modules/hal_rpi_pico/CMakeLists.txt

@@ -61,6 +61,7 @@ if(CONFIG_HAS_RPI_PICO)
  ${rp2_common_dir}/hardware_pll/pll.c
  ${rp2_common_dir}/hardware_xosc/xosc.c
  ${rp2_common_dir}/hardware_watchdog/watchdog.c
+ ${rp2_common_dir}/hardware_ticks/ticks.c
  ${rp2_common_dir}/pico_bootrom/bootrom.c
  ${rp2xxx_dir}/pico_platform/platform.c
  )