fixes for supporting multiple net ifaces on eth_mcux

zephyrproject-rtos · Jul 6, 2023 · c4b9f46 · c4b9f46
1 parent 6954375
commit c4b9f46
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Showing 2 changed files with 39 additions and 8 deletions.
diff --git a/drivers/ethernet/Kconfig.mcux b/drivers/ethernet/Kconfig.mcux
@@ -36,6 +36,14 @@ config ETH_MCUX_RMII_EXT_CLK
 	  Setting this option will configure MCUX clock block to feed RMII
 	  reference clock from external source (ENET_1588_CLKIN)
 
+config ETH_MCUX_REFCLK_50MHZ
+	bool "Configure PHY Refclk Crystal is 50MHz (else 25MHz)"
+	default n if ETH_MCUX_RMII_EXT_CLK
+	default y
+	help
+	  Setting this option will configure the PHY for a 50MHz refclk.
+
+
 config ETH_MCUX_NO_PHY_SMI
 	bool "Do not use SMI for PHY communication"
 	help

diff --git a/drivers/ethernet/eth_mcux.c b/drivers/ethernet/eth_mcux.c
@@ -8,6 +8,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "fsl_iomuxc.h"
 #define DT_DRV_COMPAT nxp_kinetis_ethernet
 
 /* Driver Limitations:
@@ -472,11 +473,13 @@ static void eth_mcux_phy_event(struct eth_context *context)
 			LOG_WRN("Reading PHY reg failed (status 0x%x)", res);
 			k_work_submit(&context->phy_work);
 		} else {
-			ctrl2 |= PHY_CTL2_REFCLK_SELECT_MASK;
-			ENET_StartSMIWrite(context->base, context->phy_addr,
-					   PHY_CONTROL2_REG,
-					   kENET_MiiWriteValidFrame,
-					   ctrl2);
+			if(IS_ENABLED(CONFIG_ETH_MCUX_REFCLK_50MHZ)) {
+				ctrl2 |= PHY_CTL2_REFCLK_SELECT_MASK;
+				ENET_StartSMIWrite(context->base, context->phy_addr,
+						   PHY_CONTROL2_REG,
+						   kENET_MiiWriteValidFrame,
+						   ctrl2);
+			}
 		}
 		context->phy_state = eth_mcux_phy_state_reset;
 #endif /* CONFIG_SOC_SERIES_IMX_RT */
@@ -1026,7 +1029,9 @@ static void eth_mcux_init(const struct device *dev)
 	sys_clock = CLOCK_GetFreq(kCLOCK_IpgClk);
 #endif
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay)
-	sys_clock = CLOCK_GetFreq(kCLOCK_EnetPll1Clk);
+	if(context->base == ENET2) {
+		sys_clock = CLOCK_GetFreq(kCLOCK_EnetPll1Clk);
+	}
 #endif
 #elif defined(CONFIG_SOC_SERIES_IMX_RT11XX)
 	sys_clock = CLOCK_GetRootClockFreq(kCLOCK_Root_Bus);
@@ -1059,6 +1064,16 @@ static void eth_mcux_init(const struct device *dev)
 			kENET_RxAccelProtoCheckEnabled;
 	}
 
+#ifdef CONFIG_ETH_MCUX_RMII_EXT_CLK
+	if(context->base == ENET) {
+		IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, true);
+		IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, false);
+	} else {
+		IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, true);
+		IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2TxClkOutputDir, false);
+	}
+#endif
+
 	ENET_Init(context->base,
 		  &context->enet_handle,
 		  &enet_config,
@@ -1227,6 +1242,9 @@ static enum ethernet_hw_caps eth_mcux_get_capabilities(const struct device *dev)
 #if defined(CONFIG_NET_DSA)
 		ETHERNET_DSA_MASTER_PORT |
 #endif
+#if defined(CONFIG_ETH_MCUX_PROMISCUOUS_MODE)
+		ETHERNET_PROMISC_MODE |
+#endif
 #if defined(CONFIG_ETH_MCUX_HW_ACCELERATION)
 		ETHERNET_HW_TX_CHKSUM_OFFLOAD |
 		ETHERNET_HW_RX_CHKSUM_OFFLOAD |
@@ -1256,6 +1274,8 @@ static int eth_mcux_set_config(const struct device *dev,
 			context->mac_addr[2], context->mac_addr[3],
 			context->mac_addr[4], context->mac_addr[5]);
 		return 0;
+  case ETHERNET_CONFIG_TYPE_PROMISC_MODE:
+    return 0;
 	default:
 		break;
 	}
@@ -1532,14 +1552,17 @@ static void eth_mcux_err_isr(const struct device *dev)
 #define _mcux_dma_desc __dtcm_bss_section
 #define _mcux_dma_buffer __dtcm_noinit_section
 #define _mcux_driver_buffer __dtcm_noinit_section
+#define MCUX_CACHED_BUF 0
 #elif defined(CONFIG_NOCACHE_MEMORY)
 #define _mcux_dma_desc __nocache
 #define _mcux_dma_buffer __nocache
 #define _mcux_driver_buffer
+#define MCUX_CACHED_BUF 1
 #else
 #define _mcux_dma_desc
 #define _mcux_dma_buffer
 #define _mcux_driver_buffer
+#define MCUX_CACHED_BUF 1
 #endif
 
 #if defined(CONFIG_ETH_MCUX_PHY_RESET)
@@ -1626,8 +1649,8 @@ static void eth_mcux_err_isr(const struct device *dev)
 		.txBdStartAddrAlign = eth##n##_tx_buffer_desc,		\
 		.rxBufferAlign = eth##n##_rx_buffer[0],			\
 		.txBufferAlign = eth##n##_tx_buffer[0],			\
-		.rxMaintainEnable = true,				\
-		.txMaintainEnable = true,				\
+		.rxMaintainEnable = (MCUX_CACHED_BUF == 1 ? true : false), \
+		.txMaintainEnable = (MCUX_CACHED_BUF == 1 ? true : false), \
 		ETH_MCUX_PTP_FRAMEINFO(n)				\
 	};								\
 									\