soc: add OpenHW Group CVA6 SoC

Adds support for the CVA6 family of RISC-V CPUs.
CVA6 is commonly found as a soft core CPU on FPGA designs.
Different configurations and instruction set extensions can be
configured, and different SoCs targeting various FPGA boards are
available.
This commit adds support for the 32-bit and 64-bit configurations
of CVA6, as well as three slightly different SoCs (a minimal 32-bit
configuration, a 64-bit configuration without FPU, a 64-bit
configuration with FPU).

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>

dts/riscv/openhwgroup/cv32a6.dtsi

@@ -0,0 +1,34 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright 2024 CISPA Helmholtz Center for Information Security
+ */
+
+#include "cva6.dtsi"
+
+/*
+ * Least common denominator of CVA6 32-bit CPUs: no FPU, no compressed instructions,
+ * no MMU, no PMP.
+ * Boards can overwrite the node if additional configurations are available.
+ */
+/ {
+	cpus_0: cpus {
+		timebase-frequency = <25000000>;
+
+		cpu_0: cpu {
+			clock-frequency = <50000000>;
+			device_type = "cpu";
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv32ima";
+			status="okay";
+
+			hlic: interrupt-controller {
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+				status="okay";
+			};
+		};
+	};
+};

dts/riscv/openhwgroup/cv64a6.dtsi

@@ -0,0 +1,36 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright 2024 CISPA Helmholtz Center for Information Security
+ */
+
+#include "cva6.dtsi"
+/*
+ * Application-class configuration of CVA6 64-bit CPUs:
+ * FPU for 32-bit and 64-bit floats, SV39 MMU.
+ *
+ */
+/ {
+	cpus_0: cpus {
+		timebase-frequency = <25000000>;
+
+		cpu_0: cpu {
+			clock-frequency = <50000000>;
+			device_type = "cpu";
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			tlb-split;
+
+			status="okay";
+
+			hlic: interrupt-controller {
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+				status="okay";
+			};
+		};
+	};
+};

dts/riscv/openhwgroup/cva6.dtsi

@@ -0,0 +1,191 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright 2024 CISPA Helmholtz Center for Information Security
+ */
+
+/*
+ * CVA6 SoC without CPU, which comes in 32 and 64 bit variants
+ */
+
+/ {
+	#address-cells = <0x01>;
+	#size-cells = <0x01>;
+
+	clocks {
+
+		clk_cpu {
+			#clock-cells = <0x00>;
+			clock-frequency = <50000000>;
+			compatible = "fixed-clock";
+		};
+
+		clk_bus: clk_bus_0 {
+			#clock-cells = <0x00>;
+			clock-frequency = <50000000>;
+			compatible = "fixed-clock";
+		};
+	};
+
+	soc {
+	#address-cells = <0x01>;
+	#size-cells = <0x01>;
+	ranges;
+
+	/* Xilinx MIG memory controller */
+	memory0:memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+		status="okay";
+	};
+
+	/* RISC-V Platform-level interrupt controller */
+	plic: interrupt-controller@c000000 {
+		compatible = "sifive,plic-1.0.0";
+		#address-cells = <0>;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		interrupts-extended = <&hlic 11 &hlic 9>;
+		reg = <0x0c000000 0x4000000>;
+		riscv,max-priority = <7>;
+		riscv,ndev = <30>;
+		status = "okay";
+	};
+
+	/* USB UART */
+	uart0:serial@10000000 {
+		clock-frequency = <50000000>;
+		clocks = <&clk_bus>;
+		compatible = "ns16550";
+		current-speed = <115200>;
+		device_type = "serial";
+		reg = <0x10000000 0x10000>;
+		reg-shift = <0x02>;
+		parity = "none";
+		stop-bits = "1";
+		data-bits = <8>;
+
+		interrupt-parent = <&plic>;
+		interrupts = <11 0x04>;
+
+		status="okay";
+	};
+
+	/* SPI controller, connected to SD card */
+	spi0: axi_quad_spi@20000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		compatible = "xlnx,xps-spi-2.00.a";
+		reg = <0x20000000 0x10000>;
+		xlnx,num-ss-bits = <0x01>;
+		xlnx,num-transfer-bits = <0x8>;
+		interrupts=<10 4>;
+		interrupt-parent=<&plic>;
+		clocks=<&clk_bus>;
+
+		status="okay";
+	};
+
+	/*
+	 * Core-local interrupt controller
+	 * Clic in zephyr terminology, clint in CVA6
+	 */
+	clint: clint_wrapper_verilog@2000000 {
+		compatible = "sifive,clint0";
+		reg = <0x2000000 0x40000>;
+		interrupts-extended = <&hlic 3 &hlic 7>;
+
+		status="okay";
+	};
+
+	/*
+	 * Xilinx AXI Ethernet subsystem and DMA.
+	 * Only on CISPA fork of the project.
+	 */
+	dma0: dma@41e00000 {
+		#dma-cells = <0x01>;
+		clock-frequency = <50000000>;
+		clock-names = "s_axi_lite_aclk";
+		clocks = <&clk_bus>;
+		compatible = "xlnx,eth-dma";
+		reg = <0x41e00000 0x10000>;
+		xlnx,addrwidth = <0x40>;
+		xlnx,include-dre;
+		xlnx,num-queues = <0x1>;
+
+		interrupt-parent = <&plic>;
+		// TX - RX
+		// active-high level-triggered
+		interrupts = <8 4>, <9 4>;
+		// TX and RX
+		dma-channels = <2>;
+
+		status="disabled";
+	};
+
+	axi-ethernet-subsystem@40c00000 {
+		reg = <0x40c00000 0x40000>;
+		compatible = "xlnx,axi-ethernet-subsystem-7.2";
+
+		eth0: ethernet-mac{
+		axistream-connected = <&dma0>;
+		axistream-control-connected = <&dma0>;
+		clock-frequency = <50000000>;
+		compatible = "xlnx,axi-ethernet-7.2";
+		local-mac-address = [00 0a 35 00 00 00]; /* change this in board device tree */
+		device_type = "network";
+		phy-mode = "rgmii";
+
+		/* full checksum offloading enabled */
+		xlnx,rxcsum = <0x2>;
+		xlnx,txcsum = <0x2>;
+
+		interrupt-parent = <&plic>;
+		interrupts = <13 4>;
+
+		status="disabled";
+		};
+
+		mdio0: mdio {
+		compatible = "xlnx,axi-ethernet-7.2-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clock-frequency = <50000000>;
+		};
+	};
+
+	/*
+	 * LowRISC ethernet subsystem.
+	 * Only on OpenHW Group original project.
+	 */
+	eth: lowrisc-eth@30000000 {
+		compatible = "lowrisc-eth";
+		device_type = "network";
+		interrupt-parent = <&plic>;
+		interrupts = <3 0>;
+		local-mac-address = [00 18 3e 02 e3 7f]; /* change this in board device tree */
+		reg = <0x0 0x30000000 0x0 0x8000>;
+	};
+
+	/* Xilinx GPIO, connected to LEDs */
+	xlnx_gpio: gpio@40000000 {
+		#gpio-cells = <2>;
+		compatible = "xlnx,xps-gpio-1.00.a";
+		gpio-controller ;
+		reg = <0x0 0x40000000 0x0 0x10000 >;
+		xlnx,all-inputs = <0x0>;
+		xlnx,all-inputs-2 = <0x0>;
+		xlnx,dout-default = <0x0>;
+		xlnx,dout-default-2 = <0x0>;
+		xlnx,gpio-width = <0x8>;
+		xlnx,gpio2-width = <0x8>;
+		xlnx,is-dual = <0x1>;
+		xlnx,tri-default = <0xffffffff>;
+		xlnx,tri-default-2 = <0xffffffff>;
+
+		status="disabled";
+	};
+
+	};
+};

soc/openhwgroup/cva6/CMakeLists.txt

@@ -0,0 +1,17 @@
+# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})
+
+if(CONFIG_SOC_FAMILY_CVA6_PROVIDE_TEST_POWEROFF)
+    # need to force the linker to keep the symbol, such that the Ariane testbench can find it
+    set(CMAKE_EXE_LINKER_FLAGS "-u tohost" CACHE INTERNAL "" FORCE)
+endif()
+
+zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_CVA6_PROVIDE_TEST_POWEROFF soc_poweroff.c)
+zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS soc_cache_management.c)
+
+
+zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_CVA6_PROVIDE_FPGA_POWEROFF soc_poweroff_fpga.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/openhwgroup/cva6/Kconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_OPENHWGROUP_CVA6
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_OPENHWGROUP_CVA6

soc/openhwgroup/cva6/Kconfig.defconfig

@@ -0,0 +1,27 @@
+# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_OPENHWGROUP_CVA6
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 25000000
+
+config RISCV_SOC_INTERRUPT_INIT
+	default y
+
+config RISCV_GP
+	default y
+
+config 2ND_LVL_ISR_TBL_OFFSET
+	default 13
+
+config 2ND_LVL_INTR_00_OFFSET
+	default 11
+
+config MAX_IRQ_PER_AGGREGATOR
+	default 186
+
+config NUM_IRQS
+	default 186
+
+endif # SOC_FAMILY_OPENHWGROUP_CVA6

soc/openhwgroup/cva6/Kconfig.soc

@@ -0,0 +1,30 @@
+#Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+#SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_OPENHWGROUP_CVA6
+	bool
+	help
+	  CVA6 RISC-V CPUs, commonly used as soft cores on FPGAs.
+	  There is a 64-bit version with imafdc extensions and sv39 MMU and
+	  several 32-bit configurations, optionally with up to imafdc and sv32 MMU.
+
+config SOC_FAMILY
+	default "ariane_cva6" if SOC_FAMILY_OPENHWGROUP_CVA6
+
+
+config SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS
+	bool "Include non-standard cache management operations (currently global cache disable)"
+	depends on SOC_FAMILY_OPENHWGROUP_CVA6
+	default n
+
+config SOC_FAMILY_CVA6_PROVIDE_TEST_POWEROFF
+	bool "Include methods for terminating a test in the CV32a6 test harness (hardware simulation)"
+	depends on SOC_FAMILY_OPENHWGROUP_CVA6
+	default n
+
+config SOC_FAMILY_CVA6_PROVIDE_FPGA_POWEROFF
+	bool "Include methods for terminating a test on the FPGA"
+	depends on SOC_FAMILY_OPENHWGROUP_CVA6
+	default n
+
+rsource "*/Kconfig.soc"

soc/openhwgroup/cva6/cv32a6/CMakeLists.txt

@@ -0,0 +1,6 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources()
+
+zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_OPENHWGROUP_CVA6 ".")

soc/openhwgroup/cva6/cv32a6/Kconfig

@@ -0,0 +1,22 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+# RISCV32 OpenHW Group cva6 configuration options
+
+config SOC_CV32A6
+	select RISCV
+	select RISCV_PRIVILEGED
+	select ATOMIC_OPERATIONS_BUILTIN
+	select RISCV_GP
+	select RISCV_HAS_PLIC
+	select USE_SWITCH_SUPPORTED
+	select USE_SWITCH
+	select CPU_HAS_FPU
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select SCHED_IPI_SUPPORTED
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
+	select HAS_POWEROFF
+	select CPU_HAS_DCACHE
+	select CPU_HAS_ICACHE