Augmenting sgw2 board pull request

Signed-off-by: Johan Kopra <johan.kopra@sensoan.com>

boards/sensoan/sgw2/CMakeLists.txt

@@ -8,16 +8,4 @@
 if(CONFIG_BOARD_SGW2_NRF9160)
 zephyr_library()
 zephyr_library_sources(nrf5340_reset.c)
-
-elseif ((CONFIG_BOARD_SGW2_NRF5340_CPUAPP OR CONFIG_BOARD_SGW2_NRF5340_CPUAPP_NS)
-    AND CONFIG_BOARD_ENABLE_CPUNET)
-zephyr_library()
-zephyr_library_sources(nrf5340_cpunet_reset.c)
-
-if (CONFIG_BUILD_WITH_TFM)
-  zephyr_library_include_directories(
-    $<TARGET_PROPERTY:tfm,TFM_BINARY_DIR>/install/interface/include
-  )
-endif()
-
 endif()

boards/sensoan/sgw2/Kconfig

@@ -27,26 +27,9 @@ config BOARD_ENABLE_DCDC_NET
 	select SOC_DCDC_NRF53X_NET
 	default y
 
-config BOARD_ENABLE_CPUNET
-	bool "NRF53 Network MCU"
-	select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \
-		$(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER))
-	help
-	  This option enables releasing the Network 'force off' signal, which
-	  as a consequence will power up the Network MCU during system boot.
-	  Additionally, the option allocates GPIO pins that will be used by UARTE
-	  of the Network MCU.
-	  Note: GPIO pin allocation can only be configured by the secure Application
-	  MCU firmware, so when this option is used with the non-secure version of
-	  the board, the application needs to take into consideration, that the
-	  secure firmware image must already have configured GPIO allocation for the
-	  Network MCU.
-	default y if (BT || NRF_802154_SER_HOST)
-
 config DOMAIN_CPUNET_BOARD
 	string
 	default "sgw2/nrf5340/cpunet"
-	depends on BOARD_ENABLE_CPUNET
 	help
 	  The board which will be used for CPUNET domain when creating a multi
 	  image application where one or more images should be located on

boards/sensoan/sgw2/board.h

@@ -36,4 +36,4 @@
  */
 #define SGW_PSEL(_FUN, _TYPE, _PIN) NRF_PSEL(_FUN, PORT(_TYPE, _PIN), PIN(_TYPE, _PIN))
 
-#endif /* BOARD_H */
+#endif /* BOARD_H */

boards/sensoan/sgw2/doc/index.rst

@@ -13,21 +13,21 @@ which is compatible with e.g. the TE Connectivity 2041119-2 board edge
 connector.
 
 
-.. figure:: img/sgw2.png
+.. figure:: img/sgw2.jpg
    :width: 500px
    :align: center
    :alt: SGW-2
 
    SGW-2 (Credit: Sensoan Oy)
 
-.. figure:: img/sgw2_pinouts.png
+.. figure:: img/sgw2_pinouts.jpg
    :width: 500px
    :align: center
    :alt: SGW-2 pinout
 
    SGW-2 pinout (Credit: Sensoan Oy)
 
-.. figure:: img/edge_connector.png
+.. figure:: img/edge_connector.jpg
    :align: center
    :alt: TE Connectivity 2041119-2
 
@@ -261,7 +261,7 @@ the lack of an info text indicates an IO that can be freely configured.
 Pins 7-9 correspond to onboard RGB leds and pin 11 correponds to an onboard
 button (a copper colored circle in the middle near the side containing the
 edge connector), and the external pins can be used e.g. for connecting
-external LEDs and buttons having the same roles as the onboard ones. 
+external LEDs and buttons having the same roles as the onboard ones.
 
 +------------+---------------+------------------------------------------------+-------------+-------------+
 | Edge pin   | Name          | Info                                           | nrf9160 pin | nrf5340 pin |
@@ -388,4 +388,4 @@ pins of each SoC (see the table above).
 Logs are by default transmitted via UART whose TX and RX are connected
 respectively to edge connector pins 22 and 23 in the case of nrf9160,
 to pins 24 and 25 in the case of nrf5340/cpuapp and to pins 26 and 29
-in the case of nrf5340/cpunet.  
+in the case of nrf5340/cpunet.

boards/sensoan/sgw2/nrf5340_cpuapp_common.dtsi

@@ -91,65 +91,10 @@
 	cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
 };
 
-&flash0 {
-
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		boot_partition: partition@0 {
-			label = "mcuboot";
-			reg = <0x00000000 0x00010000>;
-		};
-		slot0_partition: partition@10000 {
-			label = "image-0";
-		};
-		slot0_ns_partition: partition@50000 {
-			label = "image-0-nonsecure";
-		};
-		slot1_partition: partition@80000 {
-			label = "image-1";
-		};
-		slot1_ns_partition: partition@c0000 {
-			label = "image-1-nonsecure";
-		};
-		scratch_partition: partition@f0000 {
-			label = "image-scratch";
-			reg = <0x000f0000 0xa000>;
-		};
-		storage_partition: partition@fa000 {
-			label = "storage";
-			reg = <0x000fa000 0x00006000>;
-		};
-	};
-};
-
 zephyr_udc0: &usbd {
 	compatible = "nordic,nrf-usbd";
 	status = "okay";
 };
 
-/ {
-
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		sram0_image: image@20000000 {
-			/* Zephyr image(s) memory */
-		};
-
-		sram0_s: image_s@20000000 {
-			/* Secure image memory */
-		};
-
-		sram0_ns: image_ns@20040000 {
-			/* Non-Secure image memory */
-		};
-	};
-};
-
-/* Include partition configuration file */
-#include "nrf5340_cpuapp_partition_conf.dtsi"
+/* Include default memory partition configuration file */
+#include <common/nordic/nrf5340_cpuapp_partition.dtsi>

boards/sensoan/sgw2/sgw2_nrf5340.h

@@ -45,4 +45,4 @@
 #define EDGE_CONN_PORT_52 0
 #define EDGE_CONN_PIN_52  12
 
-#endif /* SGW2_NRF5340_H */
+#endif /* SGW2_NRF5340_H */

boards/sensoan/sgw2/sgw2_nrf5340_cpuapp_ns.dts

@@ -14,7 +14,7 @@
 	compatible = "sensoan,sgw2-nrf5340-cpuapp";
 
 	chosen {
-		zephyr,sram = &sram0_ns;
+		zephyr,sram = &sram0_ns_app;
 		zephyr,flash = &flash0;
 		zephyr,code-partition = &slot0_ns_partition;
 	};

boards/sensoan/sgw2/sgw2_nrf5340_cpunet.dts

@@ -94,5 +94,5 @@
 	};
 };
 
-/* Include shared RAM configuration file */
-#include "nrf5340_shared_sram_planning_conf.dtsi"
+/* Include default shared RAM configuration file */
+#include <common/nordic/nrf5340_shared_sram_partition.dtsi>

boards/sensoan/sgw2/sgw2_nrf9160.h

@@ -63,4 +63,4 @@
 #define EDGE_CONN_PORT_48 0
 #define EDGE_CONN_PIN_48  12
 
-#endif /* SGW2_NRF9160_H */
+#endif /* SGW2_NRF9160_H */