Add pinctrl driver for Quicklogic EOS S3

boards/arm/qomu/qomu.dts

@@ -6,6 +6,7 @@
 
 /dts-v1/;
 #include <quicklogic/quicklogic_eos_s3.dtsi>
+#include <zephyr/dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h>
 
 / {
 	model = "QuickLogic Qomu board";
@@ -56,6 +57,35 @@
 	};
 };
 
+&pinctrl {
+	uart1_rx_default: uart1_rx_default {
+		pinmux = <UART_RX_PAD45>;
+		input-enable;
+	};
+	uart1_tx_default: uart1_tx_default {
+		pinmux = <UART_TX_PAD44>;
+		output-enable;
+	};
+	usb_pu_default: usb_pu_default {
+		pinmux = <USB_PU_CTRL_PAD23>;
+		bias-high-impedance;
+		quicklogic,control-selection = "fabric";
+		output-enable;
+	};
+	usb_dn_default: usb_dn_default {
+		pinmux = <USB_DN_PAD28>;
+		bias-high-impedance;
+		quicklogic,control-selection = "fabric";
+		output-enable;
+	};
+	usb_dp_default: usb_dp_default {
+		pinmux = <USB_DP_PAD31>;
+		bias-high-impedance;
+		quicklogic,control-selection = "fabric";
+		output-enable;
+	};
+};
+
 &cpu0 {
 	clock-frequency = <61440000>;
 };
@@ -71,4 +101,7 @@
 &uart1 {
 	status = "okay";
 	current-speed = <115200>;
+	pinctrl-0 = <&uart1_rx_default &uart1_tx_default
+		     &usb_pu_default &usb_dn_default &usb_dp_default>;
+	pinctrl-names = "default";
 };

boards/arm/quick_feather/quick_feather.dts

@@ -6,6 +6,7 @@
 
 /dts-v1/;
 #include <quicklogic/quicklogic_eos_s3.dtsi>
+#include <zephyr/dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h>
 
 / {
 	model = "QuickLogic Quick Feather board";
@@ -56,6 +57,17 @@
 	};
 };
 
+&pinctrl {
+	uart_rx_default: uart_rx_default {
+		pinmux = <UART_RX_PAD45>;
+		input-enable;
+	};
+	uart_tx_default: uart_tx_default {
+		pinmux = <UART_TX_PAD44>;
+		output-enable;
+	};
+};
+
 &cpu0 {
 	clock-frequency = <61440000>;
 };
@@ -67,4 +79,6 @@
 &uart0 {
 	status = "okay";
 	current-speed = <115200>;
+	pinctrl-0 = <&uart_rx_default &uart_tx_default>;
+	pinctrl-names = "default";
 };

drivers/pinctrl/CMakeLists.txt

@@ -33,3 +33,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_K3 pinctrl_ti_k3.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_EMSDP pinctrl_emsdp.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_CC32XX pinctrl_ti_cc32xx.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_NUMAKER pinctrl_numaker.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_QUICKLOGIC_EOS_S3 pinctrl_eos_s3.c)

drivers/pinctrl/Kconfig

@@ -62,5 +62,6 @@ source "drivers/pinctrl/Kconfig.ti_k3"
 source "drivers/pinctrl/Kconfig.emsdp"
 source "drivers/pinctrl/Kconfig.ti_cc32xx"
 source "drivers/pinctrl/Kconfig.numaker"
+source "drivers/pinctrl/Kconfig.eos_s3"
 
 endif # PINCTRL

drivers/pinctrl/Kconfig.eos_s3

@@ -0,0 +1,9 @@
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config PINCTRL_QUICKLOGIC_EOS_S3
+	bool "QuickLogic EOS S3 SoC pinctrl driver"
+	default y
+	depends on DT_HAS_QUICKLOGIC_EOS_S3_PINCTRL_ENABLED
+	help
+	  Enable driver for the QuickLogic EOS S3 SoC pinctrl driver

drivers/pinctrl/pinctrl_eos_s3.c

@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT quicklogic_eos_s3_pinctrl
+
+#include <zephyr/arch/cpu.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h>
+#include <soc.h>
+
+LOG_MODULE_REGISTER(pinctrl_eos_s3, CONFIG_PINCTRL_LOG_LEVEL);
+
+#define FUNCTION_REGISTER(func)	(func >> 13)
+#define PAD_FUNC_SEL_MASK	GENMASK(2, 0)
+#define PAD_CTRL_SEL_BIT0	3
+#define PAD_CTRL_SEL_BIT1	4
+#define PAD_OUTPUT_EN_BIT	5
+#define PAD_PULL_UP_BIT		6
+#define PAD_PULL_DOWN_BIT	7
+#define PAD_DRIVE_STRENGTH_BIT0	8
+#define PAD_DRIVE_STRENGTH_BIT1	9
+#define PAD_SLEW_RATE_BIT	10
+#define PAD_INPUT_EN_BIT	11
+#define PAD_SCHMITT_EN_BIT	12
+
+/*
+ * Program IOMUX_func_SEL register.
+ */
+static int pinctrl_eos_s3_input_selection(uint32_t pin, uint32_t sel_reg)
+{
+	volatile uint32_t *reg = (uint32_t *)IO_MUX_BASE;
+
+	if (sel_reg <= IO_MUX_MAX_PAD_NR || sel_reg > IO_MUX_REG_MAX_OFFSET) {
+		return -EINVAL;
+	}
+	reg += sel_reg;
+	*reg = pin;
+
+	return 0;
+}
+
+/*
+ * Program IOMUX_PAD_x_CTRL register.
+ */
+static int pinctrl_eos_s3_set(uint32_t pin, uint32_t func)
+{
+	volatile uint32_t *reg = (uint32_t *)IO_MUX_BASE;
+
+	if (pin > IO_MUX_REG_MAX_OFFSET) {
+		return -EINVAL;
+	}
+	reg += pin;
+	*reg = func;
+
+	return 0;
+}
+
+static int pinctrl_eos_s3_configure_pin(const pinctrl_soc_pin_t *pin)
+{
+	uint32_t reg_value = 0;
+
+	/* Set function. */
+	reg_value |= (pin->iof & PAD_FUNC_SEL_MASK);
+
+	/* Output enable is active low. */
+	WRITE_BIT(reg_value, PAD_OUTPUT_EN_BIT, pin->output_enable ? 0 : 1);
+
+	/* These are active high. */
+	WRITE_BIT(reg_value, PAD_INPUT_EN_BIT, pin->input_enable);
+	WRITE_BIT(reg_value, PAD_SLEW_RATE_BIT, pin->slew_rate);
+	WRITE_BIT(reg_value, PAD_SCHMITT_EN_BIT, pin->schmitt_enable);
+	WRITE_BIT(reg_value, PAD_CTRL_SEL_BIT0, pin->control_selection & BIT(0));
+	WRITE_BIT(reg_value, PAD_CTRL_SEL_BIT1, pin->control_selection & BIT(1));
+
+	switch (pin->drive_strength) {
+	case 2:
+		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 0);
+		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 0);
+		break;
+	case 4:
+		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 1);
+		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 0);
+		break;
+	case 8:
+		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 0);
+		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 1);
+		break;
+	case 12:
+		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 1);
+		WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 1);
+		break;
+	default:
+		LOG_ERR("Selected drive-strength is not supported: %d\n", pin->drive_strength);
+	}
+
+	/* Enable pull-up by default; overwrite if any setting was chosen. */
+	WRITE_BIT(reg_value, PAD_PULL_UP_BIT, 1);
+	WRITE_BIT(reg_value, PAD_PULL_DOWN_BIT, 0);
+	if (pin->high_impedance) {
+		WRITE_BIT(reg_value, PAD_PULL_UP_BIT, 0);
+	} else if (pin->pull_up | pin->pull_down) {
+		WRITE_BIT(reg_value, PAD_PULL_UP_BIT, pin->pull_up);
+		WRITE_BIT(reg_value, PAD_PULL_DOWN_BIT, pin->pull_down);
+	}
+
+	/* Program registers. */
+	pinctrl_eos_s3_set(pin->pin, reg_value);
+	if (pin->input_enable && FUNCTION_REGISTER(pin->iof)) {
+		pinctrl_eos_s3_input_selection(pin->pin, FUNCTION_REGISTER(pin->iof));
+	}
+	return 0;
+}
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
+{
+	ARG_UNUSED(reg);
+
+	for (int i = 0; i < pin_cnt; i++) {
+		pinctrl_eos_s3_configure_pin(&pins[i]);
+	}
+
+	return 0;
+}

drivers/serial/Kconfig.pl011

@@ -7,6 +7,7 @@ menuconfig UART_PL011
 	depends on DT_HAS_ARM_PL011_ENABLED || DT_HAS_ARM_SBSA_UART_ENABLED
 	select SERIAL_HAS_DRIVER
 	select SERIAL_SUPPORT_INTERRUPT
+	select PINCTRL if SOC_EOS_S3
 	help
 	  This option enables the UART driver for the PL011
 

drivers/serial/Kconfig.ql_usbserialport_s3b

@@ -8,5 +8,6 @@ config UART_QUICKLOGIC_USBSERIALPORT_S3B
 	default y
 	depends on DT_HAS_QUICKLOGIC_USBSERIALPORT_S3B_ENABLED
 	select SERIAL_HAS_DRIVER
+	select PINCTRL
 	help
 	  This option enables the QuickLogic USBserialport_S3B serial driver.

dts/arm/quicklogic/quicklogic_eos_s3.dtsi

@@ -64,6 +64,11 @@
 			pin-secondary-config = <0x00>;
 			gpio-controller;
 		};
+
+		pinctrl: pinctrl@40004c00 {
+			compatible = "quicklogic,eos-s3-pinctrl";
+			reg = <0x40004c00 0x1b0>;
+		};
 	};
 };