drivers: clock_control: Added PLL fractional mode for STM32U5 #62739
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Based on RM0456, each PLL in the STM32U5 has the capability to work either in integer or fractional mode. In this update, the fractional mode can be enabled by setting the fracn value in the device tree. Signed-off-by: Jatty Andriean <jandriea@outlook.com>
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...rivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_hse_fracn_160.overlay
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| @@ -24,3 +24,7 @@ tests: | |||
| extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_160.overlay" | |||
| # Build only as HSE not implemened on available boards | |||
| build_only: true | |||
| drivers.stm32_clock_configuration.u5.sysclksrc_pll_hse_fracn_160: | |||
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What about using HSI as PLL input which would allow a "runable" test ?
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I can add a test case using HSI with a fraction value of 0. Just to make sure that it still generates the correct PLL output. I will think about any other cases later. But for now, I can only suggest using HSI with a fraction value of 0. Perhaps, you have some test cases in mind?
Added a test case that generates a 160 MHz system clock using a 16777216 Hz HSE clock and also using a 16 MHz HSI Signed-off-by: Jatty Andriean <jandriea@outlook.com>
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Hi @jandriea! To celebrate this milestone and showcase your contribution, we'd love to award you the Zephyr Technical Contributor badge. If you're interested, please claim your badge by filling out this form: Claim Your Zephyr Badge. Thank you for your valuable input, and we look forward to seeing more of your contributions in the future! 🪁 |
Based on RM0456, each PLL in the STM32U5 has the capability to work either in integer or fractional mode. In this update, the fractional mode can be enabled by setting the
fracnvalue in the device tree. This update also includes a test case that generates a 160 MHz system clock using a 16777216 Hz HSE clock.