Add virtual Cortex-R8 platform

MAINTAINERS.yml

@@ -5283,6 +5283,8 @@ Testing with Renode:
     - fkokosinski
   files:
     - cmake/emu/renode.cmake
+    - soc/renode/
+    - boards/renode/
     - boards/**/*/support/*.repl
     - boards/**/*/support/*.resc
   labels:

arch/arm/core/cortex_a_r/Kconfig

@@ -93,6 +93,14 @@ config CPU_CORTEX_R7
 	help
 	  This option signifies the use of a Cortex-R7 CPU
 
+config CPU_CORTEX_R8
+	bool
+	select CPU_AARCH32_CORTEX_R
+	select ARMV7_R
+	select ARMV7_R_FP if CPU_HAS_FPU
+	help
+	  This option signifies the use of a Cortex-R8 CPU
+
 config CPU_CORTEX_R52
 	bool
 	select CPU_AARCH32_CORTEX_R

boards/renode/cortex_r8_virtual/Kconfig.cortex_r8_virtual

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_CORTEX_R8_VIRTUAL
+	select SOC_CORTEX_R8_VIRTUAL

boards/renode/cortex_r8_virtual/board.cmake

@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+set(SUPPORTED_EMU_PLATFORMS renode)
+set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/cortex_r8_virtual.resc)
+set(RENODE_UART sysbus.uart0)

boards/renode/cortex_r8_virtual/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: cortex_r8_virtual
+  vendor: renode
+  socs:
+  - name: cortex_r8_virtual

boards/renode/cortex_r8_virtual/cortex_r8_virtual.dts

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2024 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <cortex_r8_virt.dtsi>
+
+/ {
+	model = "Cortex-R8 Virtual target";
+	compatible = "renode,cortex-r8-virtual";
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <99999901>;
+};

boards/renode/cortex_r8_virtual/cortex_r8_virtual.yaml

@@ -0,0 +1,18 @@
+identifier: cortex_r8_virtual
+name: Cortex R8 Virtual Board
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+ram: 131072
+simulation: renode
+simulation_exec: renode
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+  renode:
+    uart: sysbus.uart0
+    resc: boards/renode/cortex_r8_virtual/support/cortex_r8_virtual.resc
+supported:
+  - uart

boards/renode/cortex_r8_virtual/cortex_r8_virtual_defconfig

@@ -0,0 +1,22 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+CONFIG_ISR_STACK_SIZE=512
+CONFIG_THREAD_STACK_INFO=y
+
+CONFIG_MAX_DOMAIN_PARTITIONS=24
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable serial port
+CONFIG_UART_XLNX_PS=y
+
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+CONFIG_ARM_MPU=y

boards/renode/cortex_r8_virtual/doc/index.rst

@@ -0,0 +1,62 @@
+.. _cortex_r8_virtual:
+
+Cortex-R8 Virtual
+#################
+
+Overview
+********
+
+The Cortex-R8 Virtual board is a virtual platform that can be emulated with Renode.
+Edit the :zephyr_file:`boards/renode/cortex_r8_virtual/support/cortex_r8_virtual.repl` file to adapt the platform layout to your needs.
+
+Refer to the `Renode documentation <https://renode.readthedocs.io/en/latest/>`_
+to learn how to obtain Renode for your host.
+
+Programming and debugging
+*************************
+
+Building
+========
+
+Applications for the ``cortex_r8_virtual`` board target can be built
+using the standard build flow (see :ref:`build_an_application`):
+
+.. zephyr-app-commands::
+   :board: cortex_r8_virtual
+   :goals: build
+
+Flashing
+========
+
+Your software will run in simulation and you don't need to "flash" the board in a traditional way,
+but you can use this configuration to run Zephyr applications
+and kernel tests directly in Renode with the use of the ``run`` command.
+
+For example, with the :zephyr:code-sample:`synchronization` sample:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: cortex_r8_virtual
+   :goals: run
+
+This will build an image with the synchronization sample app, boot it using
+Renode, and display the following console output:
+
+.. code-block:: console
+
+        *** Booting Zephyr OS build v3.6.0-5689-g2a5c606abfa7 ***
+        thread_a: Hello World from cpu 0 on cortex_r8_virtual!
+        thread_b: Hello World from cpu 0 on cortex_r8_virtual!
+        thread_a: Hello World from cpu 0 on cortex_r8_virtual!
+        thread_b: Hello World from cpu 0 on cortex_r8_virtual!
+
+Exit Renode by pressing :kbd:`CTRL+C`.
+
+Debugging
+=========
+
+Refer to the detailed overview about :ref:`application_debugging`.
+
+Renode can serve as a GDB server. For more information, refer to the
+`Renode documentation about GDB debugging <https://renode.readthedocs.io/en/latest/debugging/gdb.html>`_.

boards/renode/cortex_r8_virtual/support/cortex_r8_virtual.repl

@@ -0,0 +1,31 @@
+cpu: CPU.ARMv7R @ sysbus
+    cpuType: "cortex-r8"
+    genericInterruptController: gic
+    numberOfMPURegions: 24
+    cpuId: 0
+
+scu: Miscellaneous.ArmSnoopControlUnit @ sysbus 0xae000000
+
+gic: IRQControllers.ARM_GenericInterruptController @ {
+        sysbus new Bus.BusMultiRegistration { address: 0xf9001000; size: 0x100; region: "cpuInterface" };
+        sysbus new Bus.BusMultiRegistration { address: 0xf9000000; size: 0x1000; region: "distributor" }
+    }
+    [0,1] -> cpu@[0,1]
+    architectureVersion: IRQControllers.ARM_GenericInterruptControllerVersion.GICv1
+    supportsTwoSecurityStates: false
+
+privateTimer0: Timers.ARM_PrivateTimer @ {
+        sysbus new Bus.BusPointRegistration { address: 0xae000600; cpu: cpu }
+    }
+    -> gic#0@29
+    frequency: 667000000
+
+mem: Memory.MappedMemory @ sysbus 0x0
+    size: 0x8000000
+
+uart0: UART.Cadence_UART @ sysbus 0xff000000
+    -> gic@21
+
+ttc0: Timers.Cadence_TTC @ sysbus 0xff110000
+    [0-2] -> gic@[36-38]
+    frequency: 5000000

boards/renode/cortex_r8_virtual/support/cortex_r8_virtual.resc

@@ -0,0 +1,18 @@
+:name: Cortex-R8-Virtual
+:description: This script is prepared to run Zephyr on a virtual Cortex-R8 board.
+
+$name?="Cortex-R8-Virtual"
+
+using sysbus
+mach create $name
+machine LoadPlatformDescription $ORIGIN/cortex_r8_virtual.repl
+
+
+showAnalyzer uart0
+cpu PerformanceInMips 5
+
+macro reset
+"""
+    sysbus LoadELF $elf
+"""
+runMacro $reset

cmake/gcc-m-cpu.cmake

@@ -68,6 +68,15 @@ if("${ARCH}" STREQUAL "arm")
     else()
       set(GCC_M_CPU ${GCC_M_CPU}+nofp)
     endif()
+  elseif(CONFIG_CPU_CORTEX_R8)
+    set(GCC_M_CPU cortex-r8)
+    if(CONFIG_FPU AND CONFIG_CPU_HAS_VFP)
+      if(NOT CONFIG_VFP_FEATURE_DOUBLE_PRECISION)
+        set(GCC_M_CPU ${GCC_M_CPU}+nofp.dp)
+      endif()
+    else()
+      set(GCC_M_CPU ${GCC_M_CPU}+nofp)
+    endif()
   elseif(CONFIG_CPU_CORTEX_R52)
     set(GCC_M_CPU cortex-r52)
     if(CONFIG_FPU AND CONFIG_CPU_HAS_VFP)

cmake/gcc-m-fpu.cmake

@@ -7,7 +7,7 @@ if(CONFIG_FPU)
 
 if("${ARCH}" STREQUAL "arm")
   if(CONFIG_CPU_AARCH32_CORTEX_R)
-    if(CONFIG_CPU_CORTEX_R4 OR CONFIG_CPU_CORTEX_R5) # VFPv3
+    if(CONFIG_CPU_CORTEX_R4 OR CONFIG_CPU_CORTEX_R5 OR CONFIG_CPU_CORTEX_R8) # VFPv3
       if(CONFIG_VFP_FEATURE_DOUBLE_PRECISION)
         set(GCC_M_FPU vfpv3-d16)
       elseif(CONFIG_VFP_FEATURE_SINGLE_PRECISION)

dts/arm/cortex_r8_virt.dtsi

@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2024 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r8f";
+			reg = <0>;
+		};
+	};
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = < &gic >;
+		flash0: flash@c0000000 {
+			compatible = "soc-nv-flash";
+			reg = < 0xc0000000 0x2000000 >;
+		};
+		sram0: memory@0 {
+			compatible = "mmio-sram";
+			reg = < 0x0 0x4000000 >;
+		};
+		uart0: uart@ff000000 {
+			compatible = "xlnx,xuartps";
+			reg = < 0xff000000 0x4c >;
+			status = "disabled";
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL
+					IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "irq_0";
+		};
+		ttc0: timer@ff110000 {
+			compatible = "xlnx,ttcps";
+			status = "okay";
+			interrupts = < 0x0 0x24 0x2 0xa0 >,
+				< 0x0 0x25 0x2 0xa0 >,
+				< 0x0 0x26 0x2 0xa0 >;
+			interrupt-names = "irq_0", "irq_1", "irq_2";
+			reg = < 0xff110000 0x1000 >;
+			clock-frequency = < 5000000 >;
+		};
+		gic: interrupt-controller@f9000000 {
+			compatible = "arm,gic-v1", "arm,gic";
+			reg = < 0xf9000000 0x1000 >, < 0xf9001000 0x100 >;
+			interrupt-controller;
+			#interrupt-cells = < 0x4 >;
+			status = "okay";
+			phandle = < 0x1 >;
+		};
+	};
+};

include/zephyr/arch/arm/cortex_a_r/mpu.h

@@ -32,7 +32,7 @@
 #define MPU_RASR_B_Pos                  0
 #define MPU_RASR_B_Msk                  (1UL << MPU_RASR_B_Pos)
 
-#if defined(CONFIG_CPU_CORTEX_R4) || defined(CONFIG_CPU_CORTEX_R5)
+#if defined(CONFIG_CPU_CORTEX_R4) || defined(CONFIG_CPU_CORTEX_R5) || defined(CONFIG_CPU_CORTEX_R8)
 #define ARM_MPU_REGION_SIZE_32B         ((uint8_t)0x04U)
 #define ARM_MPU_REGION_SIZE_64B         ((uint8_t)0x05U)
 #define ARM_MPU_REGION_SIZE_128B        ((uint8_t)0x06U)

modules/cmsis/cmsis_core_a_r.h

@@ -46,6 +46,8 @@ extern "C" {
 #include <core_cr5.h>
 #elif defined(CONFIG_CPU_CORTEX_R7)
 #include <core_cr7.h>
+#elif defined(CONFIG_CPU_CORTEX_R8)
+#include <core_cr8.h>
 #elif defined(CONFIG_CPU_CORTEX_R52)
 #include <core_cr52.h>
 #elif defined(CONFIG_CPU_AARCH32_CORTEX_A)

samples/userspace/prod_consumer/boards/cortex_r8_virtual.conf

@@ -0,0 +1 @@
+CONFIG_DYNAMIC_OBJECTS=y

soc/renode/cortex_r8_virtual/CMakeLists.txt

@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(soc.c)
+
+zephyr_sources_ifdef(
+  CONFIG_ARM_MPU
+  arm_mpu_regions.c
+)
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")

soc/renode/cortex_r8_virtual/Kconfig

@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_CORTEX_R8_VIRTUAL
+	select ARM
+	select CPU_CORTEX_R8
+	select PLATFORM_SPECIFIC_INIT
+	select CPU_HAS_ARM_MPU
+	select VFP_DP_D16

soc/renode/cortex_r8_virtual/Kconfig.defconfig

@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_CORTEX_R8_VIRTUAL
+
+config NUM_IRQS
+	default 220
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 5000000
+
+DT_CHOSEN_Z_FLASH := zephyr,flash
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+endif # SOC_CORTEX_R8_VIRTUAL

soc/renode/cortex_r8_virtual/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_CORTEX_R8_VIRTUAL
+	bool
+	help
+	  Cortex R8 Virtual system implementation
+
+config SOC
+	default "cortex_r8_virtual" if SOC_CORTEX_R8_VIRTUAL