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arch: riscv: handle interrupt level for CLIC #75581

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arch: riscv: handle interrupt level for CLIC #75581

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Commits on Sep 23, 2024

  1. arch: riscv: handle interrupt level for CLIC 

    CLIC supports mintstatus.MIL (RO) and mcause.MPIL (RW) for the current
interrupt level and the previous interrut level before a trap. Each ISR
must execute MRET to set mcause.MPIL back to mintstatus.MIL.

This commit introduces CONFIG_CLIC_SUPPORT_INTERRUPT_PREEMPTION to handle
mcause.MPIL for interrupt preemption in nested ISR, and uses
CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL to ensure ISR always switch out
with MRET.

e.g.
  With CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL=n, a context-switch in
  ISR may skip MRET in this flow:
  IRQ -> _isr_wrapper -> z_riscv_switch() -> retrun to arch_switch()

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
    @jimmyzhe
    jimmyzhe committed Sep 23, 2024
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  2. soc: gd32: gd32vf103: keep the mcause.interrupt by SOC-specific context 

    For Nuclei ECLIC, the interrupt level (mintstatus.MIL) is restored from
the previous interrupt level (mcause.MPIL) only if mcause.interrupt is set.
This behavior is not defined in the RISC-V CLIC spec.
If an ISR causes a context switch and mcause.interrupt is not set in the
next context (e.g. the next context is yielded from ecall), interrupts will
be masked after MRET because the interrupt level is not restored.

Use SOC-specific context to set mcause.interrupt to ensure the interrupt
level is restored correctly.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
    @jimmyzhe
    jimmyzhe committed Sep 23, 2024
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