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MCXW71 base enablement #77434
MCXW71 base enablement #77434
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The following west manifest projects have been modified in this Pull Request:
Note: This message is automatically posted and updated by the Manifest GitHub Action. |
# SPDX-License-Identifier: Apache-2.0 | ||
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zephyr_library() |
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file can go
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Change request is specifically over the lack of doc pages, if I have somehow missed them please feel free to dismiss it
dts/arm/nxp/nxp_mcxw71.dtsi
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fast_peripheral: peripheral@58000000 { |
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I'm confused here- why define fast_peripheral
and peripheral
? Are there peripherals that can be declared under fast_peripheral
and peripheral
? If not, why not just define all the peripherals under peripheral
- it seems like we only need the ranges
property for secure vs nonsecure mode.
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right now there isn't a practical reason, the purpose had nothing to do with the ranges property, it's just because according to the RM these are different peripheral buses with different sets of masters who can access them so I just felt it might be useful for something down the line to capture this aspect of the hardware in DT
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I'd prefer we group these, unless there's a strong reason not to. That will make the nonsecure definition of this part a little simpler, and is consistent with our other M33 SOCs.
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ok, I was thinking the cortex-m3 DTS would then be able to delete the &fast_peripheral bus node to have an accurate DT since it can't access that bridge but it looks like in the public RM it says even though the radio subsystem is documented pretty well and is very flexible, that the firmware programmed to the radio NBU is intended to be developed by NXP ? so maybe we don't want to support the M3 target for this chip on zephyr anyways, so we can pretend that there is not two peripheral bridges for the DT if it's that important
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Ah, that is quite a good reason. I'm fine to keep it as is then
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i'll just change it for now because I don't think we will have the m3 target any time soon, if ever
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FYI, On W71, the m3 target is not supposed to be open, so we shouldn't consider it as a target for zephyr.
It will be different on W72, where the NBU will run on a CM33+nodsp+nofpu and will be open.
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Add driver for newer SCG clock control peripheral. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add support for SCG K4 clock control in kinetis pinctrl. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add SOC DTS for MCXW71. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add MCXW71 SOC, which inherits some qualitiies of kinetis heritage platforms. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add FRDM-MCXW71 initial board. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add support for flash_k4 api from the mcux SDK. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Enable flash controller driver for main FMU on MCXW71 Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
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MCXW71 SOC base enablement