boards: openhwgroup: add CV64A6 on GenesysII board

[WorldofJARcraft]

Adds support for the CVA6 CPU on a GenesysII FPGA board with Xilinx AXI Ethernet
(https://github.com/cispa/CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet). The SoC currently contains the CVA6 CPU in 64-bit configuration with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the Xilinx AXI Ethernet subsystem.

[WorldofJARcraft]

Depends on #77732 and #73986

[nordicjm]

empty file can go

[nordicjm]

this file is not acceptable

[WorldofJARcraft]

I have cleaned the defconfigs and removed the empty CMakeLists.txt for my three board PRs.

[Dri99]

I am currently using it for a school project, if it can help, the fact that the board is called in some places cv64a6_genesysII_cispa and others cv64a6_genesysII without the "_cispa" suffix gave issues in cmake identifying the files. I fixed by renaming files adding the suffix, but consider also to just remove it everywhere

[WorldofJARcraft]

I am currently using it for a school project, if it can help, the fact that the board is called in some places cv64a6_genesysII_cispa and others cv64a6_genesysII without the "_cispa" suffix gave issues in cmake identifying the files. I fixed by renaming files adding the suffix, but consider also to just remove it everywhere

#77792 and this PR refer to two slightly different configurations.
This one uses the Xilinx Ethernet subsystem, while #77792 uses the lowRISC Ethernet (which currently does not have a driver in zephyr).
The files are adapted for these two different configurations respectively. You can use the -b parameter to west build to select which variant you want to build (-b cv64a6_genesysII or -b cv64a6_genesysII_cispa).

[WorldofJARcraft]

Merged into #77732