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drivers: mipi_dbi: add support for parallel 8080/6800 modes using GPIO #78453

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stgloorious
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Introduce GPIO-based driver for MIPI DBI class that allows MIPI DBI type A and B displays to be used on general platforms. Until now, only Type C (SPI-based) MIPI DBI displays and some SoC-specific peripherals are supported for the mipi-dpi driver class.

Since each data pin GPIO can be selected individually in the device tree, the data bus pins are set in a loop for each transmitted byte. Obviously this has a significant negative impact on performance, however, it enables maximum flexbility and compatibility with all kinds of systems.

When using 8-bit mode and all the data GPIO pins are on the same port, a data port look-up table is generated automatically to set the whole port at once as a performance optimization. This creates a RAM overhead of about 1 kiB, and is only implemented for 8-bit mode as the table grows exponentially with bus width. To me, it seems like a reasonable tradeoff between RAM overhead and performance as MCUs beefy enough to run a such a TFT display usually have enough RAM to spare.

I tested the 8-bit 8080 mode with a ILI9486 display shield on a Nordic nRF52840-DK board. The other modes are untested.

Any comments or feedback are appreciated.

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Hello @stgloorious, and thank you very much for your first pull request to the Zephyr project!
Our Continuous Integration pipeline will execute a series of checks on your Pull Request commit messages and code, and you are expected to address any failures by updating the PR. Please take a look at our commit message guidelines to find out how to format your commit messages, and at our contribution workflow to understand how to update your Pull Request. If you haven't already, please make sure to review the project's Contributor Expectations and update (by amending and force-pushing the commits) your pull request if necessary.
If you are stuck or need help please join us on Discord and ask your question there. Additionally, you can escalate the review when applicable. 😊

Instead of always using the SPI MIPI DBI mode (type C), look up the
mipi-mode from the device tree and only set the mode to
MIPI_DBI_MODE_SPI_4WIRE as a fallback in case the property is not given.

Signed-off-by: Stefan Gloor <code@stefan-gloor.ch>
@stgloorious stgloorious force-pushed the stgloorious/mipi-dbi-gpio branch 2 times, most recently from e273b49 to 5f4758c Compare September 15, 2024 23:44
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@danieldegrasse danieldegrasse left a comment

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Very cool, thanks for this! Please take a look at the compliance failure when you get a chance (you can amend commits and force push over this branch to respond to review requests/fix compliance issues)

image

drivers/display/display_ili9xxx.c Show resolved Hide resolved
drivers/mipi_dbi/Kconfig.gpio Outdated Show resolved Hide resolved
drivers/mipi_dbi/mipi_dbi_gpio.c Outdated Show resolved Hide resolved
drivers/mipi_dbi/mipi_dbi_gpio.c Outdated Show resolved Hide resolved
doc/hardware/peripherals/mipi_dbi.rst Show resolved Hide resolved
drivers/mipi_dbi/mipi_dbi_gpio.c Outdated Show resolved Hide resolved
drivers/mipi_dbi/mipi_dbi_gpio.c Outdated Show resolved Hide resolved
drivers/mipi_dbi/mipi_dbi_gpio.c Outdated Show resolved Hide resolved
@stgloorious
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Hi @danieldegrasse, thank you very much for your review. I should have addressed all the issues mentioned by you or the CI. I'll update again if there are still CI problems once it runs through.

Let me know what you think about the changes and if you think anything else could be improved.

The MIPI DBI API supports MIPI DBI controllers type A, B, and C
(except with 16 write clocks). Update the documentation accordingly.

Signed-off-by: Stefan Gloor <code@stefan-gloor.ch>
Introduce GPIO-based driver for MIPI DBI class that allows MIPI DBI
type A and B displays to be used on general platforms.

Since each data pin GPIO can be selected individually, the bus pins are
set in a loop, which has a significant negative impact on performance.
When using 8-bit mode and all the data GPIO pins are on the same port,
a look-up table is generated to set the whole port at once as a
performance optimization. This creates a ROM overhead of about 1 kiB.

Tested 8-bit 8080 mode with ILI9486 display on nRF52840-DK board.

Signed-off-by: Stefan Gloor <code@stefan-gloor.ch>
@stgloorious
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screenshot-Mo 16 Sep 2024 22:29:40 CEST

The CI doesn't like the documentation change. What am I doing wrong?

@stgloorious
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It failed again with the new forced push in check-valid-pr. For some reason it checks the old commit 30aa0d4 against the current HEAD 61130c7, and that seems to fail because probably headroom <= 1. Maybe just rerunning helps?

@danieldegrasse
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It failed again with the new forced push in check-valid-pr. For some reason it checks the old commit 30aa0d4 against the current HEAD 61130c7, and that seems to fail because probably headroom <= 1. Maybe just rerunning helps?

That is odd, I haven't seen this check fail before. I'll investigate if it fails again there

@mmahadevan108 mmahadevan108 merged commit 2571ae8 into zephyrproject-rtos:main Sep 20, 2024
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Hi @stgloorious!
Congratulations on getting your very first Zephyr pull request merged 🎉🥳. This is a fantastic achievement, and we're thrilled to have you as part of our community!

To celebrate this milestone and showcase your contribution, we'd love to award you the Zephyr Technical Contributor badge. If you're interested, please claim your badge by filling out this form: Claim Your Zephyr Badge.

Thank you for your valuable input, and we look forward to seeing more of your contributions in the future! 🪁

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5 participants