Switch to SC version 0.24.0 (#248)

examples/axi/test.py

@@ -100,7 +100,7 @@ def build_testbench():
  dut = SbDut('axi_ram', autowrap=True, cmdline=True, extra_args=extra_args,
  parameters=parameters, interfaces=interfaces, resets=resets)
 
- dut.register_package_source(
+ dut.register_source(
  'verilog-axi',
  'git+https://github.com/alexforencich/verilog-axi.git',
  '38915fb'

examples/axil/test.py

@@ -93,7 +93,7 @@ def build_testbench():
  dut = SbDut('axil_ram', autowrap=True, cmdline=True, extra_args=extra_args,
  parameters=parameters, interfaces=interfaces, resets=resets)
 
- dut.register_package_source(
+ dut.register_source(
  'verilog-axi',
  'git+https://github.com/alexforencich/verilog-axi.git',
  '38915fb'

examples/fpga_loopback/test.py

@@ -63,7 +63,7 @@ def build_testbench(fast=False):
  dut.set('tool', tool, 'task', 'compile', 'var', 'pins_bv', '2')
 
  # libsystemctlm-soc configuration
- dut.register_package_source(
+ dut.register_source(
  'libsystemctlm-soc',
  'git+https://github.com/Xilinx/libsystemctlm-soc.git',
  '670d73c'

examples/network/test.py

@@ -134,7 +134,7 @@ def make_axil_ram(net):
  dut = net.make_dut('axil_ram', parameters=parameters,
  interfaces=interfaces, resets=resets)
 
- dut.register_package_source(
+ dut.register_source(
  'verilog-axi',
  'git+https://github.com/alexforencich/verilog-axi.git',
  '38915fb'

requirements.txt

@@ -10,7 +10,7 @@
 
 numpy
 tqdm
-siliconcompiler <0.24.0
+siliconcompiler >= 0.24.0
 
 # Testing dependencies
 #:test

switchboard/sbdut.py

@@ -235,6 +235,8 @@ def __init__(
 
  self.set('option', 'builddir', str(Path(builddir).resolve()))
 
+ self.set('option', 'clean', True) # preserve old behavior
+
  self.set('option', 'mode', 'sim')
 
  if not subcomponent:
@@ -252,7 +254,7 @@ def __init__(
  self.add('option', opt, sb_path() / 'verilog' / 'common')
 
  if trace:
- self.set('option', 'trace', True)
+ self.set('tool', 'verilator', 'task', 'compile', 'var', 'trace', True)
  self.add('option', 'define', 'SB_TRACE')
 
  if self.trace_type == 'fst':

switchboard/sc/morty/uniquify.py

@@ -2,6 +2,7 @@
 # This code is licensed under Apache License 2.0 (see LICENSE for details)
 
 from .morty import setup as setup_tool
+from siliconcompiler.tools._common import get_tool_task
 
 
 def setup(chip):
@@ -13,7 +14,7 @@ def setup(chip):
  tool = 'morty'
  step = chip.get('arg', 'step')
  index = chip.get('arg', 'index')
- task = chip._get_task(step, index)
+ _, task = get_tool_task(chip, step, index)
 
  chip.set('tool', tool, 'task', task, 'var', 'suffix',
  'suffix to be added to the end of module names',
@@ -28,7 +29,7 @@ def runtime_options(chip):
  tool = 'morty'
  step = chip.get('arg', 'step')
  index = chip.get('arg', 'index')
- task = chip._get_task(step, index)
+ _, task = get_tool_task(chip, step, index)
  design = chip.top()
 
  cmdlist = []

switchboard/sc/sed/remove.py

@@ -2,6 +2,7 @@
 # This code is licensed under Apache License 2.0 (see LICENSE for details)
 
 from .sed import setup as setup_tool
+from siliconcompiler.tools._common import get_tool_task
 
 
 def setup(chip):
@@ -12,7 +13,7 @@ def setup(chip):
  tool = 'sed'
  step = chip.get('arg', 'step')
  index = chip.get('arg', 'index')
- task = chip._get_task(step, index)
+ _, task = get_tool_task(chip, step, index)
 
  chip.set('tool', tool, 'task', task, 'var', 'to_remove',
  'strings to remove from the Verilog source file',
@@ -23,7 +24,7 @@ def runtime_options(chip):
  tool = 'sed'
  step = chip.get('arg', 'step')
  index = chip.get('arg', 'index')
- task = chip._get_task(step, index)
+ _, task = get_tool_task(chip, step, index)
  design = chip.top()
 
  infile = f'inputs/{design}.v'