simplify macro usage

examples/axi/testbench.sv

@@ -38,7 +38,7 @@ module testbench (
 
     // Instantiate switchboard module
 
-    `SB_AXI_M(sb_axi_m_i, axi, clk, DATA_WIDTH, ADDR_WIDTH, ID_WIDTH, "axi");
+    `SB_AXI_M(axi, DATA_WIDTH, ADDR_WIDTH, ID_WIDTH);
 
     // Initialize RAM to zeros for easy comparison against a behavioral model
 

examples/axil/testbench.sv

@@ -36,7 +36,7 @@ module testbench (
 
     // Instantiate switchboard module
 
-    `SB_AXIL_M(sb_axil_m_i, axil, clk, DATA_WIDTH, ADDR_WIDTH, "axil");
+    `SB_AXIL_M(axil, DATA_WIDTH, ADDR_WIDTH);
 
     // Initialize RAM to zeros for easy comparison against a behavioral model
 

examples/minimal/testbench.sv

@@ -12,29 +12,31 @@ module testbench (
         `SB_CREATE_CLOCK(clk)
     `endif
 
+    localparam integer DW=256;
+
     // SB RX port
 
-    `SB_WIRES(sb_rx, 256);
-    `QUEUE_TO_SB_SIM(rx_i, sb_rx, clk, 256, "to_rtl.q");
+    `SB_WIRES(to_rtl, DW);
+    `QUEUE_TO_SB_SIM(to_rtl, DW);
 
     // SB TX port
 
-    `SB_WIRES(sb_tx, 256);
-    `SB_TO_QUEUE_SIM(tx_i, sb_tx, clk, 256, "from_rtl.q");
+    `SB_WIRES(from_rtl, DW);
+    `SB_TO_QUEUE_SIM(from_rtl, DW);
 
     // custom modification of packet
 
     genvar i;
     generate
-        for (i=0; i<32; i=i+1) begin
-            assign sb_tx_data[(i*8) +: 8] = sb_rx_data[(i*8) +: 8] + 8'd1;
+        for (i=0; i<(DW/8); i=i+1) begin
+            assign from_rtl_data[(i*8) +: 8] = to_rtl_data[(i*8) +: 8] + 8'd1;
         end
     endgenerate
 
-    assign sb_tx_dest = sb_rx_dest;
-    assign sb_tx_last = sb_rx_last;
-    assign sb_tx_valid = sb_rx_valid;
-    assign sb_rx_ready = sb_tx_ready;
+    assign from_rtl_dest = to_rtl_dest;
+    assign from_rtl_last = to_rtl_last;
+    assign from_rtl_valid = to_rtl_valid;
+    assign to_rtl_ready = from_rtl_ready;
 
     // Waveforms
 
@@ -43,7 +45,7 @@ module testbench (
     // $finish
 
     always @(posedge clk) begin
-        if (sb_rx_valid && ((&sb_rx_data) == 1'b1)) begin
+        if (to_rtl_valid && ((&to_rtl_data) == 1'b1)) begin
             $finish;
         end
     end

examples/python/testbench.sv

@@ -12,29 +12,31 @@ module testbench (
         `SB_CREATE_CLOCK(clk)
     `endif
 
+    localparam DW=256;
+
     // SB RX port
 
-    `SB_WIRES(sb_rx, 256);
-    `QUEUE_TO_SB_SIM(rx_i, sb_rx, clk, 256, "to_rtl.q");
+    `SB_WIRES(to_rtl, DW);
+    `QUEUE_TO_SB_SIM(to_rtl, DW);
 
     // SB TX port
 
-    `SB_WIRES(sb_tx, 256);
-    `SB_TO_QUEUE_SIM(tx_i, sb_tx, clk, 256, "from_rtl.q");
+    `SB_WIRES(from_rtl, DW);
+    `SB_TO_QUEUE_SIM(from_rtl, DW);
 
     // custom modification of packet
 
     genvar i;
     generate
-        for (i=0; i<32; i=i+1) begin
-            assign sb_tx_data[(i*8) +: 8] = sb_rx_data[(i*8) +: 8] + 8'd1;
+        for (i=0; i<(DW/8); i=i+1) begin
+            assign from_rtl_data[(i*8) +: 8] = to_rtl_data[(i*8) +: 8] + 8'd1;
         end
     endgenerate
 
-    assign sb_tx_dest = sb_rx_dest;
-    assign sb_tx_last = sb_rx_last;
-    assign sb_tx_valid = sb_rx_valid;
-    assign sb_rx_ready = sb_tx_ready;
+    assign from_rtl_dest = to_rtl_dest;
+    assign from_rtl_last = to_rtl_last;
+    assign from_rtl_valid = to_rtl_valid;
+    assign to_rtl_ready = from_rtl_ready;
 
     // Waveforms
 
@@ -43,7 +45,7 @@ module testbench (
     // $finish
 
     always @(posedge clk) begin
-        if (sb_rx_valid && ((&sb_rx_data) == 1'b1)) begin
+        if (to_rtl_valid && ((&to_rtl_data) == 1'b1)) begin
             $finish;
         end
     end

examples/router/testbench.sv

@@ -12,15 +12,17 @@ module testbench (
         `SB_CREATE_CLOCK(clk)
     `endif
 
+    localparam integer DW=256;
+
     // SB RX port
 
-    `SB_WIRES(sb_rx, 256);
-    `QUEUE_TO_SB_SIM(rx_i, sb_rx, clk, 256, "queue-5557");
+    `SB_WIRES(sb_rx, DW);
+    `QUEUE_TO_SB_SIM(sb_rx, DW, "queue-5557");
 
     // SB TX port
 
-    `SB_WIRES(sb_tx, 256);
-    `SB_TO_QUEUE_SIM(tx_i, sb_tx, clk, 256, "queue-5558");
+    `SB_WIRES(sb_tx, DW);
+    `SB_TO_QUEUE_SIM(sb_tx, DW, "queue-5558");
 
     // custom modification of packet
 

examples/stream/testbench.sv

@@ -12,15 +12,17 @@ module testbench (
         `SB_CREATE_CLOCK(clk)
     `endif
 
+    localparam integer DW=256;
+
     // SB RX port
 
-    `SB_WIRES(sb_rx, 256);
-    `QUEUE_TO_SB_SIM(rx_i, sb_rx, clk, 256, "client2rtl.q");
+    `SB_WIRES(sb_rx, DW);
+    `QUEUE_TO_SB_SIM(sb_rx, DW, "client2rtl.q");
 
     // SB TX port
 
-    `SB_WIRES(sb_tx, 256);
-    `SB_TO_QUEUE_SIM(tx_i, sb_tx, clk, 256, "rtl2client.q");
+    `SB_WIRES(sb_tx, DW);
+    `SB_TO_QUEUE_SIM(sb_tx, DW, "rtl2client.q");
 
     // custom modification of packet
 

examples/umi_endpoint/testbench.sv

@@ -19,10 +19,10 @@ module testbench (
     parameter integer AW=64;
 
     `SB_UMI_WIRES(udev_req, DW, CW, AW);
-    `QUEUE_TO_UMI_SIM(rx_i, udev_req, clk, DW, CW, AW, "to_rtl.q");
+    `QUEUE_TO_UMI_SIM(udev_req, DW, CW, AW, "to_rtl.q");
 
     `SB_UMI_WIRES(udev_resp, DW, CW, AW);
-    `UMI_TO_QUEUE_SIM(tx_i, udev_resp, clk, DW, CW, AW, "from_rtl.q");
+    `UMI_TO_QUEUE_SIM(udev_resp, DW, CW, AW, "from_rtl.q");
 
     reg nreset = 1'b0;
     wire [AW-1:0] loc_addr;

examples/umi_fifo/testbench.sv

@@ -19,10 +19,10 @@ module testbench (
     localparam integer CW=32;
 
     `SB_UMI_WIRES(udev_req, DW, CW, AW);
-    `QUEUE_TO_UMI_SIM(rx_i, udev_req, clk, DW, CW, AW, "to_rtl.q");
+    `QUEUE_TO_UMI_SIM(udev_req, DW, CW, AW, "to_rtl.q");
 
     `SB_UMI_WIRES(udev_resp, DW, CW, AW);
-    `UMI_TO_QUEUE_SIM(tx_i, udev_resp, clk, DW, CW, AW, "from_rtl.q");
+    `UMI_TO_QUEUE_SIM(udev_resp, DW, CW, AW, "from_rtl.q");
 
     reg nreset = 1'b0;
 

examples/umi_fifo_flex/testbench.sv

@@ -20,10 +20,10 @@ module testbench (
     parameter integer CW=32;
 
     `SB_UMI_WIRES(udev_req, IDW, CW, AW);
-    `QUEUE_TO_UMI_SIM(rx_i, udev_req, clk, IDW, CW, AW, "to_rtl.q");
+    `QUEUE_TO_UMI_SIM(udev_req, IDW, CW, AW, "to_rtl.q");
 
     `SB_UMI_WIRES(udev_resp, ODW, CW, AW);
-    `UMI_TO_QUEUE_SIM(tx_i, udev_resp, clk, ODW, CW, AW, "from_rtl.q");
+    `UMI_TO_QUEUE_SIM(udev_resp, ODW, CW, AW, "from_rtl.q");
 
     reg nreset = 1'b0;
 

examples/umi_gpio/testbench.sv

@@ -21,10 +21,10 @@ module testbench (
     localparam integer OWIDTH=128;
 
     `SB_UMI_WIRES(udev_req, DW, CW, AW);
-    `QUEUE_TO_UMI_SIM(rx_i, udev_req, clk, DW, CW, AW, "to_rtl.q");
+    `QUEUE_TO_UMI_SIM(udev_req, DW, CW, AW, "to_rtl.q");
 
     `SB_UMI_WIRES(udev_resp, DW, CW, AW);
-    `UMI_TO_QUEUE_SIM(tx_i, udev_resp, clk, DW, CW, AW, "from_rtl.q");
+    `UMI_TO_QUEUE_SIM(udev_resp, DW, CW, AW, "from_rtl.q");
 
     reg nreset = 1'b0;
     wire [(IWIDTH-1):0] gpio_in;

examples/umi_splitter/testbench.sv

@@ -21,17 +21,17 @@ module testbench (
     // UMI input
 
     `SB_UMI_WIRES(umi_in, DW, CW, AW);
-    `QUEUE_TO_UMI_SIM(rx, umi_in, clk, DW, CW, AW, "in.q");
+    `QUEUE_TO_UMI_SIM(umi_in, DW, CW, AW, "in.q");
 
     // UMI output (response)
 
     `SB_UMI_WIRES(umi_resp_out, DW, CW, AW);
-    `UMI_TO_QUEUE_SIM(tx0, umi_resp_out, clk, DW, CW, AW, "out0.q");
+    `UMI_TO_QUEUE_SIM(umi_resp_out, DW, CW, AW, "out0.q");
 
     // UMI output (request)
 
     `SB_UMI_WIRES(umi_req_out, DW, CW, AW);
-    `UMI_TO_QUEUE_SIM(tx1, umi_req_out, clk, DW, CW, AW, "out1.q");
+    `UMI_TO_QUEUE_SIM(umi_req_out, DW, CW, AW, "out1.q");
 
     // UMI splitter
 

examples/umiram/testbench.sv

@@ -19,10 +19,10 @@ module testbench (
     localparam integer CW=32;
 
     `SB_UMI_WIRES(udev_req, DW, CW, AW);
-    `QUEUE_TO_UMI_SIM(rx_i, udev_req, clk, DW, CW, AW, "to_rtl.q");
+    `QUEUE_TO_UMI_SIM(udev_req, DW, CW, AW, "to_rtl.q");
 
     `SB_UMI_WIRES(udev_resp, DW, CW, AW);
-    `UMI_TO_QUEUE_SIM(tx_i, udev_resp, clk, DW, CW, AW, "from_rtl.q");
+    `UMI_TO_QUEUE_SIM(udev_resp, DW, CW, AW, "from_rtl.q");
 
     // instantiate module with UMI ports