fix: value limbs should be 1

src/cpu/bootstrap_kernel.rs

@@ -42,15 +42,16 @@ pub(crate) fn generate_bootstrap_kernel<F: Field>(state: &mut GenerationState<F>
  final_cpu_row.mem_channels[1].value[0] = F::from_canonical_usize(Segment::Code as usize); // segment
  final_cpu_row.mem_channels[2].value[0] = F::ZERO; // virt
  final_cpu_row.mem_channels[3].value[0] = F::from_canonical_usize(KERNEL.code.len()); // len
- // final_cpu_row.mem_channels[4].value = KERNEL.code_hash.map(F::from_canonical_u32);
- // final_cpu_row.mem_channels[4].value.reverse();
- /*
- keccak_sponge_log(
- state,
- MemoryAddress::new(0, Segment::Code, 0),
- KERNEL.code.clone(),
- );
- */
+
+ // final_cpu_row.mem_channels[4].value = KERNEL.code_hash.map(F::from_canonical_u32);
+ // final_cpu_row.mem_channels[4].value.reverse();
+ /*
+ keccak_sponge_log(
+ state,
+ MemoryAddress::new(0, Segment::Code, 0),
+ KERNEL.code.clone(),
+ );
+ */
  state.traces.push_cpu(final_cpu_row);
  state.traces.push_cpu(final_cpu_row);
  log::info!("Bootstrapping took {} cycles", state.traces.clock());

src/cpu/kernel/assembler.rs

@@ -9,9 +9,8 @@ pub struct Kernel {
  pub(crate) global_labels: HashMap<String, usize>,
 }
 
-//FIXME load ELF: https://github.com/risc0/risc0/blob/main/risc0/binfmt/src/elf.rs#L34
+// FIXME: impl the mips vm
 pub(crate) fn combined_kernel() -> Kernel {
- // load ELF
  Kernel {
  code: vec![],
  ordered_labels: vec![],

src/cpu/membus.rs

@@ -7,7 +7,7 @@ use crate::constraint_consumer::{ConstraintConsumer, RecursiveConstraintConsumer
 use crate::cpu::columns::CpuColumnsView;
 
 /// General-purpose memory channels; they can read and write to all contexts/segments/addresses.
-pub const NUM_GP_CHANNELS: usize = 5;
+pub const NUM_GP_CHANNELS: usize = 32;
 
 pub mod channel_indices {
  use std::ops::Range;

src/generation/mod.rs

@@ -45,7 +45,7 @@ pub struct MipsTrace {
 /// Inputs needed for trace generation. Wrap the trace record.
 #[derive(Clone, Debug, Deserialize, Serialize, Default)]
 pub struct GenerationInputs {
- mips_traces: Vec<TraceRecord>,
+ // Code, does not need to be trace record, can be a whole MIPS ELF?
 }
 
 pub fn generate_traces<F: RichField + Extendable<D>, const D: usize>(

src/memory/memory_stark.rs

@@ -29,7 +29,7 @@ use crate::witness::memory::{MemoryAddress, MemoryOp};
 pub fn ctl_data<F: Field>() -> Vec<Column<F>> {
  let mut res =
  Column::singles([IS_READ, ADDR_CONTEXT, ADDR_SEGMENT, ADDR_VIRTUAL]).collect_vec();
- res.extend(Column::singles((0..8).map(value_limb)));
+ res.extend(Column::singles((0..VALUE_LIMBS).map(value_limb)));
  res.push(Column::single(TIMESTAMP));
  res
 }
@@ -260,14 +260,14 @@ impl<F: RichField + Extendable<D>, const D: usize> Stark<F, D> for MemoryStark<F
  let addr_context = local_values[ADDR_CONTEXT];
  let addr_segment = local_values[ADDR_SEGMENT];
  let addr_virtual = local_values[ADDR_VIRTUAL];
- let value_limbs: Vec<_> = (0..8).map(|i| local_values[value_limb(i)]).collect();
+ let value_limbs: Vec<_> = (0..VALUE_LIMBS).map(|i| local_values[value_limb(i)]).collect();
 
  let next_timestamp = next_values[TIMESTAMP];
  let next_is_read = next_values[IS_READ];
  let next_addr_context = next_values[ADDR_CONTEXT];
  let next_addr_segment = next_values[ADDR_SEGMENT];
  let next_addr_virtual = next_values[ADDR_VIRTUAL];
- let next_values_limbs: Vec<_> = (0..8).map(|i| next_values[value_limb(i)]).collect();
+ let next_values_limbs: Vec<_> = (0..VALUE_LIMBS).map(|i| next_values[value_limb(i)]).collect();
 
  // The filter must be 0 or 1.
  let filter = local_values[FILTER];
@@ -317,7 +317,7 @@ impl<F: RichField + Extendable<D>, const D: usize> Stark<F, D> for MemoryStark<F
  yield_constr.constraint_transition(range_check - computed_range_check);
 
  // Enumerate purportedly-ordered log.
- for i in 0..8 {
+ for i in 0..VALUE_LIMBS {
  yield_constr.constraint_transition(
  next_is_read * address_unchanged * (next_values_limbs[i] - value_limbs[i]),
  );
@@ -337,13 +337,13 @@ impl<F: RichField + Extendable<D>, const D: usize> Stark<F, D> for MemoryStark<F
  let addr_context = local_values[ADDR_CONTEXT];
  let addr_segment = local_values[ADDR_SEGMENT];
  let addr_virtual = local_values[ADDR_VIRTUAL];
- let value_limbs: Vec<_> = (0..8).map(|i| local_values[value_limb(i)]).collect();
+ let value_limbs: Vec<_> = (0..VALUE_LIMBS).map(|i| local_values[value_limb(i)]).collect();
  let timestamp = local_values[TIMESTAMP];
 
  let next_addr_context = next_values[ADDR_CONTEXT];
  let next_addr_segment = next_values[ADDR_SEGMENT];
  let next_addr_virtual = next_values[ADDR_VIRTUAL];
- let next_values_limbs: Vec<_> = (0..8).map(|i| next_values[value_limb(i)]).collect();
+ let next_values_limbs: Vec<_> = (0..VALUE_LIMBS).map(|i| next_values[value_limb(i)]).collect();
  let next_is_read = next_values[IS_READ];
  let next_timestamp = next_values[TIMESTAMP];
 
@@ -438,7 +438,7 @@ impl<F: RichField + Extendable<D>, const D: usize> Stark<F, D> for MemoryStark<F
  yield_constr.constraint_transition(builder, range_check_diff);
 
  // Enumerate purportedly-ordered log.
- for i in 0..8 {
+ for i in 0..VALUE_LIMBS {
  let value_diff = builder.sub_extension(next_values_limbs[i], value_limbs[i]);
  let zero_if_read = builder.mul_extension(address_unchanged, value_diff);
  let read_constraint = builder.mul_extension(next_is_read, zero_if_read);

src/memory/mod.rs

@@ -4,4 +4,4 @@ pub mod segments;
 
 // TODO: Move to CPU module, now that channels have been removed from the memory table.
 pub(crate) const NUM_CHANNELS: usize = crate::cpu::membus::NUM_CHANNELS;
-pub(crate) const VALUE_LIMBS: usize = 8;
+pub(crate) const VALUE_LIMBS: usize = 1;