feat: impl register and cpu (#4)

* feat: impl register and cpu

src/cpu/bootstrap_kernel.rs

@@ -26,6 +26,8 @@ pub(crate) fn generate_bootstrap_kernel<F: Field>(state: &mut GenerationState<F>
 
  // Write this chunk to memory, while simultaneously packing its bytes into a u32 word.
  for (channel, (addr, &byte)) in chunk.enumerate() {
+ // FIXME: should all be in the MainMemory. Both instruction and memory data are located in
+ // memory section for MIPS
  let address = MemoryAddress::new(0, Segment::Code, addr);
  let write =
  mem_write_gp_log_and_fill(channel, address, state, &mut cpu_row, byte.into());

src/cpu/kernel/assembler.rs

@@ -5,9 +5,13 @@ use std::collections::HashMap;
 
 #[derive(PartialEq, Eq, Debug, Serialize, Deserialize)]
 pub struct Kernel {
+ // MIPS ELF
  pub(crate) code: Vec<u8>,
  pub(crate) code_hash: [u32; 8],
+ // For debugging purposes
  pub(crate) ordered_labels: Vec<String>,
+ // FIXME: precompiled function and global variable, like HALT PC or ecrecover
+ // should be preprocessed after loading code
  pub(crate) global_labels: HashMap<String, usize>,
 }
 

src/cpu/kernel/load_elf.rs

@@ -103,7 +103,7 @@ mod test {
 
  #[test]
  fn load_and_check_mips_elf() {
- let mut reader = BufReader::new(File::open("test-vectors/minigeth").unwrap());
+ let mut reader = BufReader::new(File::open("test-vectors/hello").unwrap());
  let mut buffer = Vec::new();
  reader.read_to_end(&mut buffer).unwrap();
  let max_mem = 0x40000000;

src/generation/mod.rs

@@ -21,8 +21,9 @@ use crate::generation::outputs::{get_outputs, GenerationOutputs};
 use crate::generation::state::GenerationState;
 use crate::witness::transition::transition;
 
+/// FIXME: useful?
 #[derive(Clone, Debug, Deserialize, Serialize, Default)]
-pub struct MipsTrace {
+pub(crate) struct MipsTrace {
  pub cycle: u32,
  pub pc: u32,
  pub next_pc: u32,
@@ -88,6 +89,7 @@ pub fn generate_traces<F: RichField + Extendable<D>, const D: usize>(
  Ok((tables, public_values, outputs))
 }
 
+/// Perform MIPS instruction and transit state
 fn simulate_cpu<F: RichField + Extendable<D>, const D: usize>(
  state: &mut GenerationState<F>,
 ) -> anyhow::Result<()> {

src/witness/memory.rs

@@ -125,16 +125,17 @@ impl MemoryOp {
  }
 }
 
+/// FIXME: all GPRs, HI, LO, EPC and page are also located in memory
 #[derive(Clone, Debug)]
 pub struct MemoryState {
  pub(crate) contexts: Vec<MemoryContextState>,
 }
 
 impl MemoryState {
  pub fn new(kernel_code: &[u8]) -> Self {
- let code_u256s = kernel_code.iter().map(|&x| x.into()).collect();
+ let code_u32s = kernel_code.iter().map(|&x| x.into()).collect();
  let mut result = Self::default();
- result.contexts[0].segments[Segment::MainMemory as usize].content = code_u256s;
+ result.contexts[0].segments[Segment::MainMemory as usize].content = code_u32s;
  result
  }
 

src/witness/transition.rs

@@ -313,6 +313,8 @@ fn try_perform_instruction<F: Field>(state: &mut GenerationState<F>) -> Result<(
 
  fill_op_flag(op, &mut row);
 
+ // FIXME: decode instruction data, and load IMM and input data into registers
+
  /*
  if state.registers.is_stack_top_read {
  let channel = &mut row.mem_channels[0];