TestBench: add 'onStepSimulate' virtual function + callback

gtestverilog/example/Counter.test.cpp

@@ -11,6 +11,12 @@ namespace {
     class Counter : public ::testing::Test {
     public:
         void SetUp() override {
+            testBench.setCallbackSimulate([this]{
+                auto& core = testBench.core();
+
+                // synchronize 'i_simulate' with 'i_clk'
+                core.i_simulate = core.i_clk;
+            });
         }
 
         void TearDown() override {
@@ -52,3 +58,14 @@ TEST_F(Counter, ShouldIncrementRepeatedly) {
 
     ASSERT_THAT(testBench.trace, MatchesTrace(traceExpected));
 }
+
+TEST_F(Counter, ShouldSimulate) {
+    testBench.reset();
+    testBench.tick(10);
+
+    const Trace traceExpected = TraceBuilder()
+        .port(i_clk).signal( "10" ).repeat(11)
+        .port(i_simulate).signal( "10" ).repeat(11);
+
+    ASSERT_THAT(testBench.trace, MatchesTrace(traceExpected));
+}

gtestverilog/example/Counter.v

@@ -3,6 +3,10 @@
 module Counter(
     input i_clk,
     input i_reset_n,
+    /* verilator lint_off UNUSED */
+    input i_simulate,
+    /* verilator lint_on UNUSED */
+
     output [15:0] o_value
 );
 

gtestverilog/lib/TestBench.h

@@ -53,12 +53,19 @@ namespace gtestverilog {
 			// evaluate core to allow combinatorial values to settle first
 			m_core->eval();
 
-			// invert clock and evaluate again
+			// invert clock
 			m_core->i_clk = (m_core->i_clk) ? 0 : 1;
+
+			// notify virtual function - to allow any simulation code to run with the new clock value
+			onStepSimulate();
+
+			// evaluate the core
 			m_core->eval();
 
+			// step is complete
 			m_stepCount += 1;
 
+			// notify virtual function - that step has completed
 			onStep();
 		}
 
@@ -83,6 +90,7 @@ namespace gtestverilog {
 		}
 
 	protected:
+		virtual void onStepSimulate() {}
 		virtual void onStep() {}
 
 	private:

gtestverilog/tools/generate_testbench.py

@@ -70,10 +70,19 @@ def write_source_file():
     source_bottom = """
         trace.append(step);
     }}
-}}
-""".format(
 
-)
+    void {name}::onStepSimulate() {{
+        if (callbackSimulate) {{
+            callbackSimulate();
+        }}
+    }}
+
+    void {name}::setCallbackSimulate(CallbackSimulate callback) {{
+        callbackSimulate = callback;
+    }}
+
+}}  // namespace
+""".format(name = args.name)
 
     with open(args.output_source, "w") as file:
         file.write("// my output source\n")
@@ -128,9 +137,16 @@ class {name} : public ::gtestverilog::TestBench<{verilated_name}> {{
     public:
 
         virtual void onStep() override;
+        virtual void onStepSimulate() override;
+
+        typedef std::function<void()> CallbackSimulate;
+        void setCallbackSimulate(CallbackSimulate callback);
 
         ::gtestverilog::Trace trace;
 
+    private:
+        CallbackSimulate callbackSimulate;
+
     }};
 }}