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Fixes failing PowerPC unit tests #1603

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Fixes failing PowerPC unit tests #1603

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6e483e0
Fixes failing PowerPC unit tests
bmourad01 May 4, 2024
6ee00e7
Fix `ldu`
bmourad01 May 9, 2024
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2 changes: 2 additions & 0 deletions plugins/powerpc/powerpc.mli
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Original file line number Diff line number Diff line change
Expand Up @@ -399,6 +399,8 @@ module Std : sig
(** imm constructor - constructs an immediate from operand *)
val imm : (op -> exp) ec

val imm16 : (op -> exp) ec

(** var constructor - constructs a variable of bitwidth *)
val var : (bitwidth -> exp) ec

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5 changes: 5 additions & 0 deletions plugins/powerpc/powerpc_dsl.ml
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Expand Up @@ -32,6 +32,11 @@ let imm signed op =
if signed then Exp.(signed @@ of_word w)
else Exp.(unsigned @@ of_word w)

let imm16 signed op =
let w = Word.of_int ~width:16 (int_of_imm op) in
if signed then Exp.(signed @@ of_word w)
else Exp.(unsigned @@ of_word w)

let signed f = f true
let unsigned f = f false

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1 change: 1 addition & 0 deletions plugins/powerpc/powerpc_dsl.mli
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Expand Up @@ -16,6 +16,7 @@ val bitwidth : int -> bitwidth
val int_of_bitwidth : bitwidth -> int

val imm : (op -> exp) ec
val imm16 : (op -> exp) ec
val var : (bitwidth -> exp) ec
val reg : (reg -> exp) -> (op -> exp) ec
val const : (bitwidth -> int -> exp) ec
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22 changes: 11 additions & 11 deletions plugins/powerpc/powerpc_load.ml
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Expand Up @@ -9,19 +9,19 @@ open Powerpc.Std
83 eb ff fc - lwz r31, -4(r11) *)
let lbz cpu ops =
let rt = unsigned cpu.reg ops.(0) in
let im = signed imm ops.(1) in
let im = signed imm16 ops.(1) in
let ra = signed cpu.reg ops.(2) in
RTL.[ rt := cpu.load (ra + im) byte; ]

let lhz cpu ops =
let rt = unsigned cpu.reg ops.(0) in
let im = signed imm ops.(1) in
let im = signed imm16 ops.(1) in
let ra = signed cpu.reg ops.(2) in
RTL.[ rt := cpu.load (ra + im) halfword; ]

let lwz cpu ops =
let rt = unsigned cpu.reg ops.(0) in
let im = signed imm ops.(1) in
let im = signed imm16 ops.(1) in
let ra = signed cpu.reg ops.(2) in
RTL.[ rt := cpu.load (ra + im) word; ]

Expand Down Expand Up @@ -57,7 +57,7 @@ let lwzx cpu ops =
85 3f ff fc lwzu r9, -4(r31) *)
let lbzu cpu ops =
let rt = unsigned cpu.reg ops.(0) in
let im = signed imm ops.(2) in
let im = signed imm16 ops.(2) in
let ra = signed cpu.reg ops.(3) in
RTL.[
rt := cpu.load (ra + im) byte;
Expand All @@ -66,7 +66,7 @@ let lbzu cpu ops =

let lhzu cpu ops =
let rt = unsigned cpu.reg ops.(0) in
let im = signed imm ops.(2) in
let im = signed imm16 ops.(2) in
let ra = signed cpu.reg ops.(3) in
RTL.[
rt := cpu.load (ra + im) halfword;
Expand All @@ -75,7 +75,7 @@ let lhzu cpu ops =

let lwzu cpu ops =
let rt = unsigned cpu.reg ops.(0) in
let im = signed imm ops.(2) in
let im = signed imm16 ops.(2) in
let ra = signed cpu.reg ops.(3) in
RTL.[
rt := cpu.load (ra + im) word;
Expand Down Expand Up @@ -122,7 +122,7 @@ let lwzux cpu ops =
a8 29 00 05 lha r1, 5(r9) *)
let lha cpu ops =
let rt = signed cpu.reg ops.(0) in
let im = signed imm ops.(1) in
let im = signed imm16 ops.(1) in
let ra = signed cpu.reg ops.(2) in
RTL.[
rt := cpu.load (ra + im) halfword;
Expand All @@ -134,7 +134,7 @@ let lha cpu ops =
eb eb 01 16 lwa r31, 276(r11) *)
let lwa cpu ops =
let rt = signed cpu.reg ops.(0) in
let im = signed imm ops.(1) in
let im = signed imm16 ops.(1) in
let ra = signed cpu.reg ops.(2) in
RTL.[
rt := cpu.load (ra + im) word;
Expand Down Expand Up @@ -168,7 +168,7 @@ let lwax cpu ops =
let lhau cpu ops =
let rt = signed cpu.reg ops.(0) in
let ra = signed cpu.reg ops.(1) in
let im = signed imm ops.(2) in
let im = signed imm16 ops.(2) in
RTL.[
rt := cpu.load (ra + im) halfword;
ra := ra + im
Expand Down Expand Up @@ -203,7 +203,7 @@ let lwaux cpu ops =
e8 29 00 08 ld r1, 8(r9) *)
let ld cpu ops =
let rt = unsigned cpu.reg ops.(0) in
let im = signed imm ops.(1) in
let im = signed imm16 ops.(1) in
let ra = signed cpu.reg ops.(2) in
RTL.[
rt := cpu.load (ra + im) doubleword;
Expand All @@ -228,7 +228,7 @@ let ldx cpu ops =
let ldu cpu ops =
let rt = unsigned cpu.reg ops.(0) in
let ra = signed cpu.reg ops.(1) in
let im = unsigned imm ops.(2) in
let im = signed imm16 ops.(2) in
RTL.[
rt := cpu.load (ra + im) doubleword;
ra := ra + im;
Expand Down
16 changes: 8 additions & 8 deletions plugins/powerpc/powerpc_store.ml
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Expand Up @@ -9,19 +9,19 @@ open Powerpc.Std
91 28 ff d4 stw r9,-44(r8) *)
let stb cpu ops =
let rs = unsigned cpu.reg ops.(0) in
let im = signed imm ops.(1) in
let im = signed imm16 ops.(1) in
let ra = signed cpu.reg ops.(2) in
RTL.[ cpu.store (ra + im) rs byte; ]

let sth cpu ops =
let rs = unsigned cpu.reg ops.(0) in
let im = signed imm ops.(1) in
let im = signed imm16 ops.(1) in
let ra = signed cpu.reg ops.(2) in
RTL.[ cpu.store (ra + im) rs halfword; ]

let stw cpu ops =
let rs = unsigned cpu.reg ops.(0) in
let im = signed imm ops.(1) in
let im = signed imm16 ops.(1) in
let ra = signed cpu.reg ops.(2) in
RTL.[ cpu.store (ra + im) rs word; ]

Expand Down Expand Up @@ -64,7 +64,7 @@ let stdx cpu ops =
94 21 ff f0 stwu r1,-16(r1) *)
let stbu cpu ops =
let rs = unsigned cpu.reg ops.(1) in
let im = signed imm ops.(2) in
let im = signed imm16 ops.(2) in
let ra = signed cpu.reg ops.(3) in
RTL.[
cpu.store (ra + im) rs byte;
Expand All @@ -73,7 +73,7 @@ let stbu cpu ops =

let sthu cpu ops =
let rs = unsigned cpu.reg ops.(1) in
let im = signed imm ops.(2) in
let im = signed imm16 ops.(2) in
let ra = signed cpu.reg ops.(3) in
RTL.[
cpu.store (ra + im) rs halfword;
Expand All @@ -82,7 +82,7 @@ let sthu cpu ops =

let stwu cpu ops =
let rs = unsigned cpu.reg ops.(1) in
let im = signed imm ops.(2) in
let im = signed imm16 ops.(2) in
let ra = signed cpu.reg ops.(3) in
RTL.[
cpu.store (ra + im) rs word;
Expand Down Expand Up @@ -138,7 +138,7 @@ let stdux cpu ops =
f8 29 00 08 std r1, 8(r9) *)
let std cpu ops =
let rs = unsigned cpu.reg ops.(0) in
let im = signed imm ops.(1) in
let im = signed imm16 ops.(1) in
let ra = signed cpu.reg ops.(2) in
RTL.[
cpu.store (ra + im) rs doubleword;
Expand All @@ -150,7 +150,7 @@ let std cpu ops =
f8 29 00 09 stdu r1, 8(r9) *)
let stdu cpu ops =
let rs = unsigned cpu.reg ops.(1) in
let im = signed imm ops.(2) in
let im = signed imm16 ops.(2) in
let ra = signed cpu.reg ops.(3) in
let ea = unsigned var doubleword in
RTL.[
Expand Down
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