update to have correct phasing with other unphased alleles (#269)

EBIvariation · Dec 18, 2024 · 379788c · 379788c
1 parent 80d1ad8
commit 379788c
Show file tree

Hide file tree

Showing 3 changed files with 9 additions and 5 deletions.
diff --git a/src/vcf/record.cpp b/src/vcf/record.cpp
@@ -1218,15 +1218,16 @@ namespace ebi
     void Record::get_phased_alleles(std::string GT, std::vector<std::string>& alleles) const
     {
         std::string delims("|/");
-        bool anyphased = false;
+        bool anyunphased = false;
         std::vector<std::string> values;
 
         if (!GT.size()) {
             return;
         }
 
-        if (GT.find('|') != std::string::npos) {
-            anyphased = true;
+        //search for other unphased allele, other than 1st one
+        if (GT.find('/', 1) != std::string::npos) {
+            anyunphased = true;
         }
 
         util::string_split_ex(GT, delims.c_str(), values, true);
@@ -1235,7 +1236,7 @@ namespace ebi
         if (allele != values.end()) {
             if (allele->at(0) != '/' && allele->at(0) != '|') {
                 //infer phasing based on other alleles phasing
-                allele->insert(0, anyphased ? "|" : "/");
+                allele->insert(0, anyunphased ? "/" : "|");
             }
             alleles.swap(values);
         }

diff --git a/test/input_files/v4.4/failed/failed_body_invalid_sample_PSL.vcf b/test/input_files/v4.4/failed/failed_body_invalid_sample_PSL.vcf
@@ -17,3 +17,4 @@
 1	1700	rs180734498	C	<DEL>,T,<DUP>	100	PASS	SVLEN=1,.,2;SVCLAIM=D,.,D	GT:PSL	0|0:.,.
 1	1800	rs180734498	C	<CNV>,T,<DEL>	100	PASS	SVLEN=2,.,1;SVCLAIM=D,.,DJ	GT:PSL	0/0:T1,T2
 1	1900	rs180734498	C	<CNV>,T,<DUP>	100	PASS	SVLEN=1,.,21;SVCLAIM=D,.,J	GT:PSL	0/0|1:T1,T2,T3
+1	1901	rs180734498	C	T	100	PASS	SVCLAIM=.	GT:PSL	/0:T1
diff --git a/test/input_files/v4.4/passed/passed_body_samples_1.vcf b/test/input_files/v4.4/passed/passed_body_samples_1.vcf
@@ -17,4 +17,6 @@
 1	900	rs180734498	C	<CNV>,T,<DUP>	100	PASS	SVLEN=1,.,21;SVCLAIM=D,.,J	GT:PSL:PSO	/0|0|1:.,T2,T3:.,1,2
 1	1700	rs180734498	C	<DEL>,T,<DUP>	100	PASS	SVLEN=1,.,2;SVCLAIM=D,.,D	GT:PSL:PSO	0/0:.,.:.,.
 1	1800	rs180734498	C	<CNV>,T,<DEL>	100	PASS	SVLEN=2,.,1;SVCLAIM=D,.,DJ	GT:PSL:PSQ	0|0:T1,T2:1,2
-1	1900	rs180734498	C	<CNV>,T,<DUP>	100	PASS	SVLEN=1,.,21;SVCLAIM=D,.,J	GT:PSL:PSQ	0/0|1:T1,.,T3:1,.,3
+1	1900	rs180734498	C	<CNV>,T,<DUP>	100	PASS	SVLEN=1,.,21;SVCLAIM=D,.,J	GT:PSL:PSQ	0/0|1:.,.,T3:.,.,3
+1	1901	rs180734498	C	T	100	PASS	SVCLAIM=.	GT:PSL:PSQ	0:T1:3
+1	1902	rs180734498	C	T	100	PASS	SVCLAIM=.	GT:PSL:PSQ	/0:.:.