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Failed Circuits #234

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135 changes: 135 additions & 0 deletions Failed Subcircuits/Log Amplifier/LOG_Amplifier-cache.lib
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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# GND
#
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# PORT
#
DEF PORT U 0 40 Y Y 26 F N
F0 "U" 50 100 30 H V C CNN
F1 "PORT" 0 0 30 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
S -100 50 100 -50 0 1 0 N
X ~ 1 250 0 100 L 30 30 1 1 B
X ~ 2 250 0 100 L 30 30 2 1 B
X ~ 3 250 0 100 L 30 30 3 1 B
X ~ 4 250 0 100 L 30 30 4 1 B
X ~ 5 250 0 100 L 30 30 5 1 B
X ~ 6 250 0 100 L 30 30 6 1 B
X ~ 7 250 0 100 L 30 30 7 1 B
X ~ 8 250 0 100 L 30 30 8 1 B
X ~ 9 250 0 100 L 30 30 9 1 B
X ~ 10 250 0 100 L 30 30 10 1 B
X ~ 11 250 0 100 L 30 30 11 1 B
X ~ 12 250 0 100 L 30 30 12 1 B
X ~ 13 250 0 100 L 30 30 13 1 B
X ~ 14 250 0 100 L 30 30 14 1 B
X ~ 15 250 0 100 L 30 30 15 1 B
X ~ 16 250 0 100 L 30 30 16 1 B
X ~ 17 250 0 100 L 30 30 17 1 B
X ~ 18 250 0 100 L 30 30 18 1 B
X ~ 19 250 0 100 L 30 30 19 1 B
X ~ 20 250 0 100 L 30 30 20 1 B
X ~ 21 250 0 100 L 30 30 21 1 B
X ~ 22 250 0 100 L 30 30 22 1 B
X ~ 23 250 0 100 L 30 30 23 1 B
X ~ 24 250 0 100 L 30 30 24 1 B
X ~ 25 250 0 100 L 30 30 25 1 B
X ~ 26 250 0 100 L 30 30 26 1 B
ENDDRAW
ENDDEF
#
# eSim_C
#
DEF eSim_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "eSim_C" 25 -100 50 H V L CNN
F2 "" 38 -150 30 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS capacitor
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 40 40 1 1 P
X ~ 2 0 -150 110 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# eSim_NPN
#
DEF eSim_NPN Q 0 0 Y N 1 F N
F0 "Q" -100 50 50 H V R CNN
F1 "eSim_NPN" -50 150 50 H V R CNN
F2 "" 200 100 29 H V C CNN
F3 "" 0 0 60 H V C CNN
ALIAS BC547 Q2N2222
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
X C 1 100 200 100 D 50 50 1 1 P
X B 2 -200 0 225 R 50 50 1 1 P
X E 3 100 -200 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# eSim_R
#
DEF eSim_R R 0 0 N Y 1 F N
F0 "R" 50 130 50 H V C CNN
F1 "eSim_R" 50 -50 50 H V C CNN
F2 "" 50 -20 30 H V C CNN
F3 "" 50 50 30 V V C CNN
ALIAS resistor
$FPLIST
R_*
Resistor_*
$ENDFPLIST
DRAW
S 150 10 -50 90 0 1 10 N
X ~ 1 -100 50 50 R 60 60 1 1 P
X ~ 2 200 50 50 L 60 60 1 1 P
ENDDRAW
ENDDEF
#
# lm_741
#
DEF lm_741 X 0 40 Y Y 1 F N
F0 "X" -200 0 60 H V C CNN
F1 "lm_741" -100 -250 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N
X off_null 1 -50 400 200 D 50 38 1 1 I
X inv 2 -550 150 200 R 50 38 1 1 I
X non_inv 3 -550 -100 200 R 50 38 1 1 I
X v_neg 4 -150 -450 200 U 50 38 1 1 I
X off_null 5 50 350 200 D 50 38 1 1 I
X out 6 550 0 200 L 50 38 1 1 O
X v_pos 7 -150 450 200 D 50 38 1 1 I
X NC 8 150 -300 200 U 50 38 1 1 N
ENDDRAW
ENDDEF
#
#End Library
18 changes: 18 additions & 0 deletions Failed Subcircuits/Log Amplifier/LOG_Amplifier.cir
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* C:\FOSSEE\eSim\library\SubcircuitLibrary\LOG_Amplifier\LOG_Amplifier.cir

* EESchema Netlist Version 1.1 (Spice format) creation date: 9/11/2022 7:52:59 PM

* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0

* Sheet Name: /
X1 ? /Inp1 GND /Vneg ? Net-_Q1-Pad3_ /Vpos ? lm_741
X2 ? /Inp2 GND /Vneg ? /Vout /Vpos ? lm_741
Q1 /Inp1 Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN
Q2 /Inp2 GND Net-_Q1-Pad3_ eSim_NPN
R1 /Vout Net-_Q1-Pad2_ 3.2k
R2 Net-_Q1-Pad2_ GND 5k
C1 /Vout /Inp2 3.4u
U1 /Inp1 /NC /Vout /Vpos /Vneg GND /NC /Inp2 PORT

.end
21 changes: 21 additions & 0 deletions Failed Subcircuits/Log Amplifier/LOG_Amplifier.cir.out
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* c:\fossee\esim\library\subcircuitlibrary\log_amplifier\log_amplifier.cir

.include lm_741.sub
.include NPN.lib
x1 ? /inp1 gnd /vneg ? net-_q1-pad3_ /vpos ? lm_741
x2 ? /inp2 gnd /vneg ? /vout /vpos ? lm_741
q1 /inp1 net-_q1-pad2_ net-_q1-pad3_ Q2N2222
q2 /inp2 gnd net-_q1-pad3_ Q2N2222
r1 /vout net-_q1-pad2_ 3.2k
r2 net-_q1-pad2_ gnd 5k
c1 /vout /inp2 3.4u
* u1 /inp1 /nc /vout /vpos /vneg gnd /nc /inp2 port
.tran 0e-00 0e-00 0e-00

* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
71 changes: 71 additions & 0 deletions Failed Subcircuits/Log Amplifier/LOG_Amplifier.pro
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update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=adc-dac
LibName2=memory
LibName3=xilinx
LibName4=microcontrollers
LibName5=dsp
LibName6=microchip
LibName7=analog_switches
LibName8=motorola
LibName9=texas
LibName10=intel
LibName11=audio
LibName12=interface
LibName13=digital-audio
LibName14=philips
LibName15=display
LibName16=cypress
LibName17=siliconi
LibName18=opto
LibName19=atmel
LibName20=contrib
LibName21=power
LibName22=eSim_Plot
LibName23=transistors
LibName24=conn
LibName25=eSim_User
LibName26=regul
LibName27=74xx
LibName28=cmos4000
LibName29=eSim_Analog
LibName30=eSim_Devices
LibName31=eSim_Digital
LibName32=eSim_Hybrid
LibName33=eSim_Miscellaneous
LibName34=eSim_Power
LibName35=eSim_Sources
LibName36=eSim_Subckt
LibName37=eSim_Nghdl
LibName38=eSim_Ngveri
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