tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.

Signed-off-by: enriquezgarc <enriquezgarcia.external@infineon.com>
Infineon · Apr 16, 2024 · 7e8da47 · 7e8da47
1 parent 8ef7037
commit 7e8da47
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/tests/psoc6/hw_ext/pwm.py b/tests/psoc6/hw_ext/pwm.py
@@ -16,7 +16,7 @@
 elif "CY8CPROTO-063-BLE" in machine:
     pwm_pin = "P12_6"
     pin_in = "P12_7"
-    duty_tolerance = 15.0
+    duty_tolerance = 20.0
 
 input_pin = Pin(pin_in, Pin.IN)