tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.

Signed-off-by: enriquezgarc <enriquezgarcia.external@infineon.com>
Infineon · Apr 16, 2024 · 8ef7037 · 8ef7037
1 parent 487f6f0
commit 8ef7037
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/tests/psoc6/hw_ext/pwm.py b/tests/psoc6/hw_ext/pwm.py
@@ -11,18 +11,19 @@
 if "CY8CPROTO-062-4343W" in machine:
     pwm_pin = "P13_7"
     pin_in = "P13_6"
+    duty_tolerance = 10.0  # Different per board to accommodate HIL limitations
 
 elif "CY8CPROTO-063-BLE" in machine:
     pwm_pin = "P12_6"
     pin_in = "P12_7"
+    duty_tolerance = 15.0
 
 input_pin = Pin(pin_in, Pin.IN)
 
 start_time = 0
 low_signal_start_time = 0
 high_signal_start_time = 0
 tolerance = 3.0
-duty_tolerance = 13.0
 debug = False