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Bitstream test #126

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merged 26 commits into from
Apr 17, 2024
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004e29b
ports/psoc6: Bitstream Tests.
IFX-Anusha Mar 20, 2024
f8a5b63
tests/psoc6: Image & cicd setup.
IFX-Anusha Mar 26, 2024
b81ac1d
tests/psoc6: Fix Ruff.
IFX-Anusha Mar 26, 2024
a32d63b
tests/psoc6: Modification for cicd.
IFX-Anusha Mar 26, 2024
1e361ee
tests/psoc6: Adding ADC setup to hil.
NikhitaR-IFX Apr 1, 2024
929df0b
tests/psoc6/bitstream: Refactoring bitstream.
jaenrig-ifx Apr 4, 2024
5580ddb
tests/psoc6/bitstream: WIP readability.
jaenrig-ifx Apr 8, 2024
abe6b8b
tests/psoc6: Code refactor.
IFX-Anusha Apr 9, 2024
77fbc86
tests/psoc6: Modification of test script.
IFX-Anusha Apr 9, 2024
0bfd4ae
tests/psoc6/hw_ext/adc.py: Generalized without pin info.
jaenrig-ifx Apr 12, 2024
b7aa996
tests/psoc6/bitstream: Refining bitstream tests.
jaenrig-ifx Apr 15, 2024
a9d855c
tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.
jaenrig-ifx Apr 16, 2024
438ac4f
tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.
jaenrig-ifx Apr 16, 2024
b826a54
tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.
jaenrig-ifx Apr 16, 2024
d1e24eb
tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.
jaenrig-ifx Apr 16, 2024
7b77ab3
tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.
jaenrig-ifx Apr 16, 2024
80a79a9
tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.
jaenrig-ifx Apr 16, 2024
e75415e
tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.
jaenrig-ifx Apr 16, 2024
76ad8bc
tests/psoc6/hw_ext/pin.py: Refactor for REPL timing performance.
jaenrig-ifx Apr 16, 2024
d74db51
tests/psoc6/hw_ext/pin.py: Refactor for REPL timing performance.
jaenrig-ifx Apr 16, 2024
4d2e243
tests/psoc6/adc: Removed redundant adc tests.
jaenrig-ifx Apr 16, 2024
8ce47cb
tests/psoc6/adc: Removed redundant adc tests.
jaenrig-ifx Apr 16, 2024
05bb30c
tests/psoc6/adc: Removed redundant adc tests.
jaenrig-ifx Apr 16, 2024
57b7021
tests/psoc6/hw_ext: Updated HIL pin diagrams.
jaenrig-ifx Apr 16, 2024
c082d4b
.github/workflows/ports_psoc6.yml: Updated required extended board ver.
jaenrig-ifx Apr 16, 2024
c39743c
tools/psoc6/ifx-mpy-hil-devs.yml: Updated boards configuration in HIL.
jaenrig-ifx Apr 16, 2024
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12 changes: 9 additions & 3 deletions .github/workflows/ports_psoc6.yml
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ jobs:
run: echo "sha_short=$(git rev-parse --short HEAD)" >> $GITHUB_OUTPUT
- name: Save firmware bin
if: success() && github.repository_owner == 'infineon'
uses: actions/upload-artifact@v3
uses: actions/upload-artifact@v4
with:
name: mpy-psoc6_${{ matrix.board }}_${{ steps.commit_sha.outputs.sha_short }}
path: ports/psoc6/build/firmware.hex
Expand All @@ -57,7 +57,7 @@ jobs:
steps:
- uses: actions/checkout@v4
- name: Download binaries
uses: actions/download-artifact@v3
uses: actions/download-artifact@v4
- name: Container setup
run: |
echo ${{ secrets.SELF_HOSTED_PASSWORD }} | sudo -S chmod 666 /var/run/docker.sock
Expand All @@ -83,9 +83,15 @@ jobs:
./psoc6/run_psoc6_tests.sh -c --psoc6 --dev0 ${devs[0]}
- name: Run psoc6 hardware extended tests
run: |
devs=($(python tools/psoc6/get-devs.py port -b ${{ matrix.board }} -y tools/psoc6/${{ runner.name }}-devs.yml --hw-ext 0.1.0))
devs=($(python tools/psoc6/get-devs.py port -b ${{ matrix.board }} -y tools/psoc6/${{ runner.name }}-devs.yml --hw-ext 0.2.0.a))
cd tests
./psoc6/run_psoc6_tests.sh -c --psoc6-hwext --dev0 ${devs[0]}
- name: Run psoc6 bitstream tests
run: |
devs0=($(python tools/psoc6/get-devs.py port -b ${{ matrix.board }} -y tools/psoc6/${{ runner.name }}-devs.yml --hw-ext 0.2.0.a))
devs1=($(python tools/psoc6/get-devs.py port -b ${{ matrix.board }} -y tools/psoc6/${{ runner.name }}-devs.yml --hw-ext 0.2.0.b))
cd tests
./psoc6/run_psoc6_tests.sh -c -b --dev0 ${devs0[0]} --dev1 ${devs1[0]}
# TODO: Enable when HIL is upgraded
# - name: Run all implemented tests
# if: github.event_name == 'pull_request'
Expand Down
26 changes: 0 additions & 26 deletions tests/psoc6/adc.py

This file was deleted.

3 changes: 0 additions & 3 deletions tests/psoc6/adc.py.exp

This file was deleted.

36 changes: 0 additions & 36 deletions tests/psoc6/adcblock.py

This file was deleted.

4 changes: 0 additions & 4 deletions tests/psoc6/adcblock.py.exp

This file was deleted.

95 changes: 95 additions & 0 deletions tests/psoc6/bitstream/bitstream_rx.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,95 @@
import os
import time
from machine import Pin
from machine import bitstream

""""
This script is running together with the bitstream_tx.py test.
One pin generates a synchronisation signal to inform the transmitter that receiver is ready, and
another is configured as an input, which is used for receiving the bitstream signals.
"""

# Allocate pin based on board
machine = os.uname().machine
if "CY8CPROTO-062-4343W" in machine:
bitstream_in_pin_name = "P12_1"
rx_ready_signal_pin_name = "P13_5"

elif "CY8CPROTO-063-BLE" in machine:
bitstream_in_pin_name = "P5_2"
rx_ready_signal_pin_name = "P6_2"

expected_values = [
8000,
5000,
8000,
5000,
8000,
5000,
8000,
5000,
3000,
1000,
3000,
1000,
3000,
1000,
3000,
1000,
]
tolerance = 100


def notify_readiness_to_tx():
rx_ready_signal_pin = Pin(
rx_ready_signal_pin_name, Pin.OUT, value=0
) # signal to inform the transmitter that receiver is read
rx_ready_signal_pin.low()
# delay
for i in range(1000):
pass
rx_ready_signal_pin.high()
rx_ready_signal_pin.deinit()


def bitstream_rx_measure():
global periods
periods = []
last_value = 0
bitstream_in_pin = Pin(bitstream_in_pin_name, Pin.IN)
start_time = time.ticks_us()
current_value = 0

for i in range(17):
while current_value == last_value:
current_value = bitstream_in_pin.value()
current_time = time.ticks_us()
time_period = time.ticks_diff(current_time, start_time)
last_value = current_value
start_time = current_time
periods.append(time_period)

bitstream_in_pin.deinit()


def validate_bitstream():
for i in range(len(periods) - 1):
diff = abs(periods[i + 1] - expected_values[i])
if diff <= tolerance:
print("true")
else:
print("false")
print(
"expected :"
+ str(expected_values[i])
+ " period: "
+ str(periods[i + 1])
+ " diff: "
+ str(diff)
)


print("bitstream rx")
notify_readiness_to_tx()
bitstream_rx_measure()
validate_bitstream()
17 changes: 17 additions & 0 deletions tests/psoc6/bitstream/bitstream_rx.py.exp
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
bitstream rx
true
true
true
true
true
true
true
true
true
true
true
true
true
true
true
true
54 changes: 54 additions & 0 deletions tests/psoc6/bitstream/bitstream_tx.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,54 @@
import sys
import time
import os
from machine import Pin
from machine import bitstream

"""
This script is running together with the bitstream_rx.py test.
One pin generates the test bitstream pattern, and another is configured as
an input, which is used for synchronization with the receiver.
"""

# Allocate pin based on board
machine = os.uname().machine
if "CY8CPROTO-062-4343W" in machine:
bitstream_pin_name = "P12_1"
wait_signal_pin_name = "P13_5"
elif "CY8CPROTO-063-BLE" in machine:
bitstream_pin_name = "P5_2"
wait_signal_pin_name = "P6_2"

signal_received = False


def signal_irq(arg):
global signal_received
signal_received = True


def wait_for_rx_ready():
global signal_received
wait_signal_pin = Pin(wait_signal_pin_name, Pin.IN)
wait_signal_pin.irq(handler=signal_irq, trigger=Pin.IRQ_RISING)
while not signal_received:
pass

signal_received = False
wait_signal_pin.deinit()
# print("rx ready")


def send_bitstream():
timing = [3000000, 1000000, 8000000, 5000000]
buf = bytearray([0xF0])
bitstream_pin = Pin(bitstream_pin_name, Pin.OUT, value=0)
for i in range(2):
bitstream(bitstream_pin, 0, timing, buf)

bitstream_pin.deinit()


# print("bitstream tx")
wait_for_rx_ready()
send_bitstream()
35 changes: 8 additions & 27 deletions tests/psoc6/hw_ext/adc.py
Original file line number Diff line number Diff line change
Expand Up @@ -20,16 +20,11 @@
adc_pin_mid = "P10_3"
adc_pin_max = "P10_0"
adc_wrong_pin_name = "P13_7"
# Enable after DUT setup
print("SKIP")
raise SystemExit
elif "CY8CPROTO-063-BLE" in machine:
adc_pin_gnd = "P10_1"
adc_pin_gnd = "P10_2"
adc_pin_mid = "P10_3"
adc_pin_max = "P10_0"
adc_pin_max = "P10_4"
adc_wrong_pin_name = "P13_7"
print("SKIP")
raise SystemExit

# 0.35V
tolerance_uv = 350000
Expand All @@ -41,22 +36,18 @@

def validate_adc_uv_value(adc_pin, exp_volt, act_volt):
print(
"\nExpected voltage - ",
"Expected voltage - ",
exp_volt,
"(uV) on pin ",
adc_pin,
"is approx same as obtained voltage(uV): ",
"(uV) is approx same as obtained voltage(uV): ",
(exp_volt - tolerance_uv) < act_volt < (exp_volt + tolerance_uv),
)


def validate_adc_raw_value(adc_pin, exp_volt, act_volt):
print(
"\nExpected voltage - ",
"Expected voltage - ",
exp_volt,
"(raw) on pin ",
adc_pin,
"is approx same as obtained voltage(raw): ",
"(raw) is approx same as obtained voltage(raw): ",
(exp_volt - tolerance_raw) < act_volt < (exp_volt + tolerance_raw),
)

Expand All @@ -67,30 +58,23 @@ def validate_adc_raw_value(adc_pin, exp_volt, act_volt):
except:
print("Invalid ADC Pin\n")

adc0 = ADC(adc_pin_gnd, sample_ns=1000)
print(adc0)

block = ADCBlock(0, bits=12)
# ADCBlock.connect(channel)
adc1 = block.connect(3)
print("\nADCBlock.connect(channel): ", adc1)
block.deinit()
print("ADCBlock.deinit(): ", block)

# ADCBlock.connect(source)
block = ADCBlock(0, bits=12)
adc1 = block.connect(adc_pin_mid)
print("ADCBlock.connect(source): ", adc1)
block.deinit()
print("ADCBlock.deinit(): ", block)

adc0 = ADC(adc_pin_gnd, sample_ns=1000)

# ADCBlock.connect(channel,source)
block = ADCBlock(0, bits=12)
adc1 = block.connect(3, adc_pin_mid)
print("ADCBlock.connect(channel,source)", adc1)

adc2 = ADC(adc_pin_max, sample_ns=1000)
print("\n", adc2)

adc0_value_uv = adc0.read_uv()
validate_adc_uv_value(adc_pin_gnd, 0, adc0_value_uv)
Expand All @@ -108,8 +92,5 @@ def validate_adc_raw_value(adc_pin, exp_volt, act_volt):
validate_adc_raw_value(adc_pin_max, 32767, adc2_value_raw)

adc0.deinit()
print("\n", adc0)
adc1.deinit()
print(adc1)
adc2.deinit()
print(adc2)
31 changes: 6 additions & 25 deletions tests/psoc6/hw_ext/adc.py.exp
Original file line number Diff line number Diff line change
@@ -1,27 +1,8 @@
Invalid ADC Pin

<ADC Pin=81, ADCBlock_id=0, sampling_time_ns=1000>

ADCBlock.connect(channel): <ADC Pin=83, ADCBlock_id=0, sampling_time_ns=1000>
ADCBlock.deinit(): ADCBlock(0, bits=12)
ADCBlock.connect(source): <ADC Pin=83, ADCBlock_id=0, sampling_time_ns=1000>
ADCBlock.deinit(): ADCBlock(0, bits=12)
ADCBlock.connect(channel,source) <ADC Pin=83, ADCBlock_id=0, sampling_time_ns=1000>

<ADC Pin=80, ADCBlock_id=0, sampling_time_ns=1000>

Expected voltage - 0 (uV) on pin P10_1 is approx same as obtained voltage(uV): True

Expected voltage - 0 (raw) on pin P10_1 is approx same as obtained voltage(raw): True

Expected voltage - 1650000 (uV) on pin P10_3 is approx same as obtained voltage(uV): True

Expected voltage - 16385 (raw) on pin P10_3 is approx same as obtained voltage(raw): True

Expected voltage - 3300000 (uV) on pin P10_0 is approx same as obtained voltage(uV): True

Expected voltage - 32767 (raw) on pin P10_0 is approx same as obtained voltage(raw): True

<ADC Pin=81, ADCBlock_id=0, sampling_time_ns=1000>
<ADC Pin=83, ADCBlock_id=0, sampling_time_ns=1000>
<ADC Pin=80, ADCBlock_id=0, sampling_time_ns=1000>
Expected voltage - 0 (uV) is approx same as obtained voltage(uV): True
Expected voltage - 0 (raw) is approx same as obtained voltage(raw): True
Expected voltage - 1650000 (uV) is approx same as obtained voltage(uV): True
Expected voltage - 16385 (raw) is approx same as obtained voltage(raw): True
Expected voltage - 3300000 (uV) is approx same as obtained voltage(uV): True
Expected voltage - 32767 (raw) is approx same as obtained voltage(raw): True
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Why left side has v0.1.0 and right one v0.2.0?

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I feel we should have table for pin connections with a column for module name else it will start getting difficult to understand which connections are for which module. What do you think @jaenrig-ifx ?

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Yes, we need to differentiate boards with another nomenclature not just semver.
And the table is a good idea, but if you agree let´s do it once we have the whole machine modules included, that way it should be more definitive, as we still need to add the ADC, SPI, UART, SD.

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I will keep this open until I modify the HIL.
@NikhitaR-IFX if you have the ADC changes ready, you can add them here, I can try to do both at once and merge it all together.

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Yes, we need to differentiate boards with another nomenclature not just semver. And the table is a good idea, but if you agree let´s do it once we have the whole machine modules included, that way it should be more definitive, as we still need to add the ADC, SPI, UART, SD.

Yes agree

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I will keep this open until I modify the HIL. @NikhitaR-IFX if you have the ADC changes ready, you can add them here, I can try to do both at once and merge it all together.

Added now. Is it too small to be visible in proto board? I don't know why, but it seemed ok in my local. Let me know and I can try resizing accordingly.

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