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Bitstream test #126
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Bitstream test #126
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004e29b
ports/psoc6: Bitstream Tests.
IFX-Anusha f8a5b63
tests/psoc6: Image & cicd setup.
IFX-Anusha b81ac1d
tests/psoc6: Fix Ruff.
IFX-Anusha a32d63b
tests/psoc6: Modification for cicd.
IFX-Anusha 1e361ee
tests/psoc6: Adding ADC setup to hil.
NikhitaR-IFX 929df0b
tests/psoc6/bitstream: Refactoring bitstream.
jaenrig-ifx 5580ddb
tests/psoc6/bitstream: WIP readability.
jaenrig-ifx abe6b8b
tests/psoc6: Code refactor.
IFX-Anusha 77fbc86
tests/psoc6: Modification of test script.
IFX-Anusha 0bfd4ae
tests/psoc6/hw_ext/adc.py: Generalized without pin info.
jaenrig-ifx b7aa996
tests/psoc6/bitstream: Refining bitstream tests.
jaenrig-ifx a9d855c
tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.
jaenrig-ifx 438ac4f
tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.
jaenrig-ifx b826a54
tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.
jaenrig-ifx d1e24eb
tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.
jaenrig-ifx 7b77ab3
tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.
jaenrig-ifx 80a79a9
tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.
jaenrig-ifx e75415e
tests/psoc6/hw_ext/pwm.py: Refactor for REPL timing performance.
jaenrig-ifx 76ad8bc
tests/psoc6/hw_ext/pin.py: Refactor for REPL timing performance.
jaenrig-ifx d74db51
tests/psoc6/hw_ext/pin.py: Refactor for REPL timing performance.
jaenrig-ifx 4d2e243
tests/psoc6/adc: Removed redundant adc tests.
jaenrig-ifx 8ce47cb
tests/psoc6/adc: Removed redundant adc tests.
jaenrig-ifx 05bb30c
tests/psoc6/adc: Removed redundant adc tests.
jaenrig-ifx 57b7021
tests/psoc6/hw_ext: Updated HIL pin diagrams.
jaenrig-ifx c082d4b
.github/workflows/ports_psoc6.yml: Updated required extended board ver.
jaenrig-ifx c39743c
tools/psoc6/ifx-mpy-hil-devs.yml: Updated boards configuration in HIL.
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,95 @@ | ||
import os | ||
import time | ||
from machine import Pin | ||
from machine import bitstream | ||
|
||
"""" | ||
This script is running together with the bitstream_tx.py test. | ||
One pin generates a synchronisation signal to inform the transmitter that receiver is ready, and | ||
another is configured as an input, which is used for receiving the bitstream signals. | ||
""" | ||
|
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# Allocate pin based on board | ||
machine = os.uname().machine | ||
if "CY8CPROTO-062-4343W" in machine: | ||
bitstream_in_pin_name = "P12_1" | ||
rx_ready_signal_pin_name = "P13_5" | ||
|
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elif "CY8CPROTO-063-BLE" in machine: | ||
bitstream_in_pin_name = "P5_2" | ||
rx_ready_signal_pin_name = "P6_2" | ||
|
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expected_values = [ | ||
8000, | ||
5000, | ||
8000, | ||
5000, | ||
8000, | ||
5000, | ||
8000, | ||
5000, | ||
3000, | ||
1000, | ||
3000, | ||
1000, | ||
3000, | ||
1000, | ||
3000, | ||
1000, | ||
] | ||
tolerance = 100 | ||
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||
|
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def notify_readiness_to_tx(): | ||
rx_ready_signal_pin = Pin( | ||
rx_ready_signal_pin_name, Pin.OUT, value=0 | ||
) # signal to inform the transmitter that receiver is read | ||
rx_ready_signal_pin.low() | ||
# delay | ||
for i in range(1000): | ||
pass | ||
rx_ready_signal_pin.high() | ||
rx_ready_signal_pin.deinit() | ||
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||
|
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def bitstream_rx_measure(): | ||
global periods | ||
periods = [] | ||
last_value = 0 | ||
bitstream_in_pin = Pin(bitstream_in_pin_name, Pin.IN) | ||
start_time = time.ticks_us() | ||
current_value = 0 | ||
|
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for i in range(17): | ||
while current_value == last_value: | ||
current_value = bitstream_in_pin.value() | ||
current_time = time.ticks_us() | ||
time_period = time.ticks_diff(current_time, start_time) | ||
last_value = current_value | ||
start_time = current_time | ||
periods.append(time_period) | ||
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bitstream_in_pin.deinit() | ||
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|
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def validate_bitstream(): | ||
for i in range(len(periods) - 1): | ||
diff = abs(periods[i + 1] - expected_values[i]) | ||
if diff <= tolerance: | ||
print("true") | ||
else: | ||
print("false") | ||
print( | ||
"expected :" | ||
+ str(expected_values[i]) | ||
+ " period: " | ||
+ str(periods[i + 1]) | ||
+ " diff: " | ||
+ str(diff) | ||
) | ||
|
||
|
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print("bitstream rx") | ||
notify_readiness_to_tx() | ||
bitstream_rx_measure() | ||
validate_bitstream() |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,17 @@ | ||
bitstream rx | ||
true | ||
true | ||
true | ||
true | ||
true | ||
true | ||
true | ||
true | ||
true | ||
true | ||
true | ||
true | ||
true | ||
true | ||
true | ||
true |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,54 @@ | ||
import sys | ||
import time | ||
import os | ||
from machine import Pin | ||
from machine import bitstream | ||
|
||
""" | ||
This script is running together with the bitstream_rx.py test. | ||
One pin generates the test bitstream pattern, and another is configured as | ||
an input, which is used for synchronization with the receiver. | ||
""" | ||
|
||
# Allocate pin based on board | ||
machine = os.uname().machine | ||
if "CY8CPROTO-062-4343W" in machine: | ||
bitstream_pin_name = "P12_1" | ||
wait_signal_pin_name = "P13_5" | ||
elif "CY8CPROTO-063-BLE" in machine: | ||
bitstream_pin_name = "P5_2" | ||
wait_signal_pin_name = "P6_2" | ||
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signal_received = False | ||
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def signal_irq(arg): | ||
global signal_received | ||
signal_received = True | ||
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def wait_for_rx_ready(): | ||
global signal_received | ||
wait_signal_pin = Pin(wait_signal_pin_name, Pin.IN) | ||
wait_signal_pin.irq(handler=signal_irq, trigger=Pin.IRQ_RISING) | ||
while not signal_received: | ||
pass | ||
|
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signal_received = False | ||
wait_signal_pin.deinit() | ||
# print("rx ready") | ||
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def send_bitstream(): | ||
timing = [3000000, 1000000, 8000000, 5000000] | ||
buf = bytearray([0xF0]) | ||
bitstream_pin = Pin(bitstream_pin_name, Pin.OUT, value=0) | ||
for i in range(2): | ||
bitstream(bitstream_pin, 0, timing, buf) | ||
|
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bitstream_pin.deinit() | ||
|
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# print("bitstream tx") | ||
wait_for_rx_ready() | ||
send_bitstream() |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,27 +1,8 @@ | ||
Invalid ADC Pin | ||
|
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<ADC Pin=81, ADCBlock_id=0, sampling_time_ns=1000> | ||
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ADCBlock.connect(channel): <ADC Pin=83, ADCBlock_id=0, sampling_time_ns=1000> | ||
ADCBlock.deinit(): ADCBlock(0, bits=12) | ||
ADCBlock.connect(source): <ADC Pin=83, ADCBlock_id=0, sampling_time_ns=1000> | ||
ADCBlock.deinit(): ADCBlock(0, bits=12) | ||
ADCBlock.connect(channel,source) <ADC Pin=83, ADCBlock_id=0, sampling_time_ns=1000> | ||
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<ADC Pin=80, ADCBlock_id=0, sampling_time_ns=1000> | ||
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Expected voltage - 0 (uV) on pin P10_1 is approx same as obtained voltage(uV): True | ||
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Expected voltage - 0 (raw) on pin P10_1 is approx same as obtained voltage(raw): True | ||
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Expected voltage - 1650000 (uV) on pin P10_3 is approx same as obtained voltage(uV): True | ||
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Expected voltage - 16385 (raw) on pin P10_3 is approx same as obtained voltage(raw): True | ||
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Expected voltage - 3300000 (uV) on pin P10_0 is approx same as obtained voltage(uV): True | ||
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Expected voltage - 32767 (raw) on pin P10_0 is approx same as obtained voltage(raw): True | ||
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<ADC Pin=81, ADCBlock_id=0, sampling_time_ns=1000> | ||
<ADC Pin=83, ADCBlock_id=0, sampling_time_ns=1000> | ||
<ADC Pin=80, ADCBlock_id=0, sampling_time_ns=1000> | ||
Expected voltage - 0 (uV) is approx same as obtained voltage(uV): True | ||
Expected voltage - 0 (raw) is approx same as obtained voltage(raw): True | ||
Expected voltage - 1650000 (uV) is approx same as obtained voltage(uV): True | ||
Expected voltage - 16385 (raw) is approx same as obtained voltage(raw): True | ||
Expected voltage - 3300000 (uV) is approx same as obtained voltage(uV): True | ||
Expected voltage - 32767 (raw) is approx same as obtained voltage(raw): True |
Binary file modified
BIN
+1.74 MB
(200%)
tests/psoc6/hw_ext/img/cy8cproto-062-4343w-hil-test-diag.png
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Why left side has v0.1.0 and right one v0.2.0?
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I feel we should have table for pin connections with a column for module name else it will start getting difficult to understand which connections are for which module. What do you think @jaenrig-ifx ?
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Yes, we need to differentiate boards with another nomenclature not just semver.
And the table is a good idea, but if you agree let´s do it once we have the whole machine modules included, that way it should be more definitive, as we still need to add the ADC, SPI, UART, SD.
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I will keep this open until I modify the HIL.
@NikhitaR-IFX if you have the ADC changes ready, you can add them here, I can try to do both at once and merge it all together.
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Yes agree
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Added now. Is it too small to be visible in proto board? I don't know why, but it seemed ok in my local. Let me know and I can try resizing accordingly.