Bitstream test

[IFX-Anusha]

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Description

• Bitstream test setup with hardware connection. Here two boards are required for the setup.

• Bitstream_listen.py will run on one device & main.py on another device.

[github-actions]

Code size report:

   bare-arm:    +0 +0.000% 
minimal x86:    +0 +0.000% 
   unix x64:    +0 +0.000% standard
      stm32:   +48 +0.012% PYBV10
     mimxrt:   +52 +0.014% TEENSY40
        rp2:   +48 +0.014% RPI_PICO
       samd:   +48 +0.018% ADAFRUIT_ITSYBITSY_M4_EXPRESS

[NikhitaR-IFX]

Why left side has v0.1.0 and right one v0.2.0?

[NikhitaR-IFX]

I feel we should have table for pin connections with a column for module name else it will start getting difficult to understand which connections are for which module. What do you think @jaenrig-ifx ?

[jaenrig-ifx]

Yes, we need to differentiate boards with another nomenclature not just semver.
And the table is a good idea, but if you agree let´s do it once we have the whole machine modules included, that way it should be more definitive, as we still need to add the ADC, SPI, UART, SD.

[jaenrig-ifx]

I will keep this open until I modify the HIL.
@NikhitaR-IFX if you have the ADC changes ready, you can add them here, I can try to do both at once and merge it all together.

[NikhitaR-IFX]

Yes, we need to differentiate boards with another nomenclature not just semver. And the table is a good idea, but if you agree let´s do it once we have the whole machine modules included, that way it should be more definitive, as we still need to add the ADC, SPI, UART, SD.

Yes agree

[NikhitaR-IFX]

I will keep this open until I modify the HIL. @NikhitaR-IFX if you have the ADC changes ready, you can add them here, I can try to do both at once and merge it all together.

Added now. Is it too small to be visible in proto board? I don't know why, but it seemed ok in my local. Let me know and I can try resizing accordingly.