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Refactor translation and reverse translation of PipelineEnableINTEL for loops and functions #2171

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Oct 9, 2023
Merged

Refactor translation and reverse translation of PipelineEnableINTEL for loops and functions #2171

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b046edb
refactor loop and kernel pipelining metadata names
bowenxue-intel Oct 3, 2023
c0f05bf
revert loop MD translation changes, rename function MD
bowenxue-intel Oct 4, 2023
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2 changes: 1 addition & 1 deletion lib/SPIRV/SPIRVInternal.h
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Original file line number Diff line number Diff line change
Expand Up @@ -412,7 +412,7 @@ const static char PreferDSP[] = "prefer_dsp";
const static char PropDSPPref[] = "propagate_dsp_preference";
const static char InitiationInterval[] = "initiation_interval";
const static char MaxConcurrency[] = "max_concurrency";
const static char DisableLoopPipelining[] = "disable_loop_pipelining";
const static char PipelineKernel[] = "pipeline_kernel";
const static char IntelFPGAIPInterface[] = "ip_interface";
} // namespace kSPIR2MD

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4 changes: 2 additions & 2 deletions lib/SPIRV/SPIRVReader.cpp
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Expand Up @@ -4531,8 +4531,8 @@ bool SPIRVToLLVM::transFPGAFunctionMetadata(SPIRVFunction *BF, Function *F) {
if (BF->hasDecorate(DecorationPipelineEnableINTEL)) {
auto Literals = BF->getDecorationLiterals(DecorationPipelineEnableINTEL);
std::vector<Metadata *> MetadataVec;
MetadataVec.push_back(ConstantAsMetadata::get(getInt32(M, !Literals[0])));
F->setMetadata(kSPIR2MD::DisableLoopPipelining,
MetadataVec.push_back(ConstantAsMetadata::get(getInt32(M, Literals[0])));
F->setMetadata(kSPIR2MD::PipelineKernel,
MDNode::get(*Context, MetadataVec));
}
return true;
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7 changes: 3 additions & 4 deletions lib/SPIRV/SPIRVWriter.cpp
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Expand Up @@ -1029,12 +1029,11 @@ void LLVMToSPIRVBase::transFPGAFunctionMetadata(SPIRVFunction *BF,
BF->addDecorate(new SPIRVDecorateMaxConcurrencyINTEL(BF, Invocations));
}
}
if (MDNode *DisableLoopPipelining =
F->getMetadata(kSPIR2MD::DisableLoopPipelining)) {
if (MDNode *PipelineKernel = F->getMetadata(kSPIR2MD::PipelineKernel)) {
if (BM->isAllowedToUseExtension(
ExtensionID::SPV_INTEL_fpga_invocation_pipelining_attributes)) {
size_t Disable = getMDOperandAsInt(DisableLoopPipelining, 0);
BF->addDecorate(new SPIRVDecoratePipelineEnableINTEL(BF, !Disable));
size_t Pipeline = getMDOperandAsInt(PipelineKernel, 0);
BF->addDecorate(new SPIRVDecoratePipelineEnableINTEL(BF, Pipeline));
}
}

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12 changes: 6 additions & 6 deletions test/extensions/INTEL/SPV_INTEL_kernel_attributes/intel_fpga_function_attributes.ll
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Expand Up @@ -10,7 +10,7 @@
;; intel::loop_fuse_independent(3),
;; intel::initiation_interval(10),
;; intel::max_concurrency(12),
;; intel::disable_loop_pipelining]] void operator()() {}
;; intel::pipeline_kernel]] void operator()() {}
;; };
;;
;; template <typename name, typename Func>
Expand Down Expand Up @@ -62,23 +62,23 @@
; CHECK-LLVM-SAME: !stall_enable ![[ONEMD:[0-9]+]] !loop_fuse ![[FUSE:[0-9]+]]
; CHECK-LLVM-SAME: !initiation_interval ![[II:[0-9]+]]
; CHECK-LLVM-SAME: !max_concurrency ![[MAXCON:[0-9]+]]
; CHECK-LLVM-SAME: !disable_loop_pipelining ![[ONEMD]]
; CHECK-LLVM-SAME: !pipeline_kernel ![[ONEMD2:[0-9]+]]
; CHECK-LLVM-SAME: !max_work_group_size ![[MAXWG:[0-9]+]]
; CHECK-LLVM-SAME: !no_global_work_offset ![[OFFSET:[0-9]+]]
; CHECK-LLVM-SAME: !max_global_work_dim ![[ONEMD]] !num_simd_work_items ![[NUMSIMD:[0-9]+]]
; CHECK-LLVM-SAME: !scheduler_target_fmax_mhz ![[MAXMHZ:[0-9]+]]
; CHECK-LLVM-NOT: define spir_kernel void {{.*}}kernel_name2 {{.*}} !no_global_work_offset {{.*}}
; CHECK-LLVM: define spir_kernel void {{.*}}kernel_name3()
; CHECK-LLVM-SAME: !disable_loop_pipelining ![[ONEMD2:[0-9]+]]
; CHECK-LLVM-SAME: !pipeline_kernel ![[ONEMD]]
; CHECK-LLVM: ![[OFFSET]] = !{}
; CHECK-LLVM: ![[ONEMD]] = !{i32 1}
; CHECK-LLVM: ![[FUSE]] = !{i32 3, i32 1}
; CHECK-LLVM: ![[II]] = !{i32 10}
; CHECK-LLVM: ![[MAXCON]] = !{i32 12}
; CHECK-LLVM: ![[ONEMD2]] = !{i32 0}
; CHECK-LLVM: ![[MAXWG]] = !{i32 1, i32 1, i32 1}
; CHECK-LLVM: ![[NUMSIMD]] = !{i32 8}
; CHECK-LLVM: ![[MAXMHZ]] = !{i32 1000}
; CHECK-LLVM: ![[ONEMD2]] = !{i32 0}

; ModuleID = 'kernel-attrs.cpp'
source_filename = "kernel-attrs.cpp"
Expand All @@ -91,7 +91,7 @@ target triple = "spir64-unknown-linux"
$_ZN3FooclEv = comdat any

; Function Attrs: nounwind
define spir_kernel void @_ZTSZ3barvE11kernel_name() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 !num_simd_work_items !5 !max_work_group_size !6 !max_global_work_dim !7 !no_global_work_offset !4 !stall_enable !7 !scheduler_target_fmax_mhz !12 !loop_fuse !13 !initiation_interval !14 !max_concurrency !15 !disable_loop_pipelining !7 {
define spir_kernel void @_ZTSZ3barvE11kernel_name() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 !num_simd_work_items !5 !max_work_group_size !6 !max_global_work_dim !7 !no_global_work_offset !4 !stall_enable !7 !scheduler_target_fmax_mhz !12 !loop_fuse !13 !initiation_interval !14 !max_concurrency !15 !pipeline_kernel !16 {
entry:
%Foo = alloca %class._ZTS3Foo.Foo, align 1
call void @llvm.lifetime.start.p0(i64 1, ptr %Foo) #4
Expand Down Expand Up @@ -135,7 +135,7 @@ entry:
}

; Function Attrs: nounwind
define spir_kernel void @_ZTSZ3barvE11kernel_name3() #0 !disable_loop_pipelining !16 {
define spir_kernel void @_ZTSZ3barvE11kernel_name3() #0 !pipeline_kernel !7 {
entry:
%Foo = alloca %class._ZTS3Foo.Foo, align 1
call void @llvm.lifetime.start.p0(i64 1, ptr %Foo) #4
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4 changes: 2 additions & 2 deletions test/extensions/INTEL/SPV_INTEL_kernel_attributes/spirv_fpga_function_decorations.ll
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Expand Up @@ -37,9 +37,9 @@ entry:
!10 = !{i32 5919, i32 1}
!11 = !{i32 5917, i32 2}

; CHECK-SPV-IR: define spir_kernel void @k(float %a, float %b, float %c) {{.*}} !initiation_interval ![[II:[0-9]+]] !disable_loop_pipelining ![[DISABLE_LOOP_PIPELINING:[0-9]+]] {
; CHECK-SPV-IR: define spir_kernel void @k(float %a, float %b, float %c) {{.*}} !initiation_interval ![[II:[0-9]+]] !pipeline_kernel ![[PIPELINE_KERNEL:[0-9]+]] {
; CHECK-SPV-IR-DAG: ![[II]] = !{i32 2}
; CHECK-SPV-IR-DAG: ![[DISABLE_LOOP_PIPELINING]] = !{i32 0}
; CHECK-SPV-IR-DAG: ![[PIPELINE_KERNEL]] = !{i32 1}

; CHECK-LLVM-NOT: define spir_kernel void @k(float %a, float %b, float %c) {{.*}} !spirv.Decorations ![[DecoListId:[0-9]+]] {
; CHECK-LLVM: define spir_kernel void @k(float %a, float %b, float %c) {{.*}} {
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