verilog only syntax

Peter-Herrmann · Nov 4, 2023 · caebb92 · caebb92
1 parent c550b88
commit caebb92
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/wishbone/wb_to_obi.v b/wishbone/wb_to_obi.v
@@ -43,7 +43,8 @@ module wb_to_obi (
     input [31:0]        rdata_i  
     );
 
-    logic read_outstanding, write_completed, read_accepted_a, write_accepted_a;
+    reg read_outstanding, write_completed;
+    wire read_accepted_a, write_accepted_a;
     assign read_accepted_a  = (req_o && gnt_i) && !wbs_we_i;
     assign write_accepted_a = (req_o && gnt_i) && wbs_we_i;