WARNING: this is a WIP project in an early stage (Sep, 2023).
VHDL / System Verilog to Verilog converter, based on Yosys, and the plugins ghdl-yosys-plugin and synlig. It relies on Docker and PyFPGA containers.
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VHDL / System Verilog to Verilog converter, based on Yosys and the plugins ghdl-yosys-plugin and synlig.
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PyFPGA/hdl2vlog
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VHDL / System Verilog to Verilog converter, based on Yosys and the plugins ghdl-yosys-plugin and synlig.